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Add new drivers for new gpio and io_mux

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This commit is contained in:
Manuel Eggimann 2022-12-08 18:08:21 +01:00
parent d8dc704518
commit baad1c5fff
13 changed files with 8722 additions and 41 deletions
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33
drivers/gpio/gpio.c
View file

@ -2,11 +2,17 @@
#include "common/bitfield.h"
#include "gpio_hal.h"
#include "pulp.h"
#include "hal/utils.h"
void gpio_init(gpios_t* handle) {
memset(handle, 0, sizeof(gpios_t));
handle->base_addr = ARCHI_GPIO_ADDR;
}
void gpio_configure(uint32_t number, uint32_t direction){
void gpio_configure(gpios_t* handle, uint32_t number, uint32_t direction){
// Now configure the GPIO peripheral
uint32_t addr = ARCHI_GPIO_ADDR + GPIO_MODE_REG_OFFSET_BASE + number/16*4;
uint32_t addr = handle->base_addr + GPIO_MODE_REG_OFFSET_BASE + number/16*4;
uint32_t reg = archi_read32(addr);
bitfield_field32_t field;
field.mask = 0x3;
@ -14,28 +20,9 @@ void gpio_configure(uint32_t number, uint32_t direction){
reg = bitfield_field32_write(reg, field, (direction == GPIO_DIRECTION_INPUT)? GPIO_MODE_REG_VALUE_INPUT_ONLY: GPIO_MODE_REG_VALUE_OUTPUT_ACTIVE);
archi_write32(addr, reg);
// Enable/Disable input sampling
addr = ARCHI_GPIO_ADDR + GPIO_EN_INPUT_REG_OFFSET_BASE + number/32*4;
addr = handle->base_addr + GPIO_EN_INPUT_REG_OFFSET_BASE + number/32*4;
reg = archi_read32(addr);
reg = bitfield_bit32_write(reg, number%32, direction == SIRACUSA_GPIO_DIRECTION_INPUT);
reg = bitfield_bit32_write(reg, number%32, direction == GPIO_DIRECTION_INPUT);
archi_write32(addr, reg);
hal_compiler_barrier();
}
void gpio_set(uint32_t number, uint32_t value){
uint32_t addr;
if (value == 1) {
addr = ARCHI_GPIO_ADDR + GPIO_SET_REG_OFFSET_BASE + number/32*4;
} else {
addr = SIRACUSA_GPIO_BASE_ADDR + GPIO_CLEAR_REG_OFFSET_BASE + number/32*4;
}
archi_write32(addr, 1<<(number%32));
hal_compiler_barrier();
}
uint32_t gpio_get(uint32_t number){
uint32_t addr = SIRACUSA_GPIO_BASE_ADDR + GPIO_GPIO_IN_0_REG_OFFSET + number/32*4;
uint32_t reg = archi_read32(addr);
return bitfield_bit32_read(reg, number%32);
hal_compiler_barrier();
}

56
drivers/gpio/include/gpio.h
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@ -21,13 +21,33 @@
*/
#ifndef GPIO_H
#define GPIO_H
#ifndef LANGUAGE_ASSEMBLY
#include <stdint.h>
#include "common/bitfield.h"
#include "gpio_hal.h"
#include "hal/utils.h"
#include "archi/utils.h"
#define GPIO_DIRECTION_OUTPUT 1
#define GPIO_DIRECTION_INPUT 0
typedef struct {
uint32_t base_addr;
} gpios_t;
/**
* Initializes the peripheral handle structure
*
* This function must be called before using the handle for gpio interaction.
*
* @param hanlde A pointer to the handle to initialize.
*/
void gpio_init(gpios_t* handle);
/**
* Configure the provided GPIO as either an input or output.
*
@ -39,7 +59,7 @@
* @param number The GPIO number to confgiure. You can either use directly an integer number or on of the PAD_GPIOXX macros.
* @param direction Either GPIO_DIRECTION_INPUT (0) or GPIO_DIRECTION_OUTPUT
*/
void gpio_configure(uint32_t number, uint32_t direction);
void gpio_configure(gpios_t* handle, uint32_t number, uint32_t direction);
/**
* Get the current value of the GPIO.
@ -49,7 +69,12 @@ void gpio_configure(uint32_t number, uint32_t direction);
* @param number The GPIO number to confgiure. You can either use directly an integer number or on of the PAD_GPIOXX macros.
* @returns 0 if the gpio is currently at logic level LOW or 1 if it is at logic level HIGH.
*/
uint32_t gpio_get(uint32_t number);
static inline uint32_t gpio_get(gpios_t* handle, uint32_t number) {
uint32_t addr = handle->base_addr + GPIO_INPUT_REG_OFFSET_BASE + number/32*4;
uint32_t reg = archi_read32(addr);
return bitfield_bit32_read(reg, number%32);
hal_compiler_barrier();
}
/**
* Drive the GPIO to the provided value.
@ -59,6 +84,31 @@ uint32_t gpio_get(uint32_t number);
* @param number The GPIO number to confgiure. You can either use directly an integer number or on of the PAD_GPIOXX macros.
* @param value Either 0 or 1.
*/
void gpio_set(uint32_t number, uint32_t value);
static inline void gpio_set(gpios_t* handle, uint32_t number, uint32_t value) {
uint32_t addr;
if (value == 1) {
addr = handle->base_addr + GPIO_SET_REG_OFFSET_BASE + number/32*4;
} else {
addr = handle->base_addr + GPIO_CLEAR_REG_OFFSET_BASE + number/32*4;
}
archi_write32(addr, 1<<(number%32));
hal_compiler_barrier();
}
/**
* Toggle the GPIO
*
* The corresponding GPIO must have been configured as an output using configure_gpio().
*
* @param number The GPIO number to confgiure. You can either use directly an integer number or on of the PAD_GPIOXX macros.
*/
static inline void gpio_toggle(gpios_t* handle, uint32_t number) {
uint32_t addr = handle->base_addr + GPIO_TOGGLE_REG_OFFSET_BASE + number/32*4;
archi_write32(addr, 1<<(number%32));
hal_compiler_barrier();
}
#endif
#endif /* GPIO_H */

198
drivers/pulpissimo/rtl_sim/io_mux/include/io_mux.h Normal file
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@ -0,0 +1,198 @@
/*
* Copyright (C) 2021 ETH Zurich, University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Title: io_mux.h
* Author: Manuel Eggimann <meggimann@iis.ee.ethz.ch>
* Date: 25.08.2021
*
* Description: Control the pad configuration and multiplexing of the Siracusa chip
*/
#ifndef IO_MUX_H
#define IO_MUX_H
#ifndef LANGUAGE_ASSEMBLY
#include <stdint.h>
#include "pulpissimo_padframe_all_pads_regs.h"
#define IO_MUX_PAD_CFG_REG_OFFSET 0x4
#define IO_MUX_PAD_MUX_SEL_REG_OFFSET 0x8
#define IO_MUX_PAD_REG_SEPARATION 0x8
typedef enum {
IO_MUX_NO_PULL, ///< No pull resistor is enabled
IO_MUX_PULL_EN, ///< Enable internal pull-up/down (depends on pad kind) resistor
} io_mux_pull_cfg_e;
/**
* Pad configuration struct
*
* Keep in mind, that certain peripherals might take over control of certain pad
* config signals (e.g. rx_en) if connected to a pad. The settings you provide
* through this API only take effect unless not overriden by the currently
* connected peripheral.
*/
typedef struct {
io_mux_pull_cfg_e pull_cfg; ///< Pull-up/down settings of the pad
uint8_t tx_en; ///< Tx enable
uint8_t rx_en; ///< Rx enable
} io_mux_cfg_t;
/**
* Pad modes
*
* This enum defines all the different roles a particular IO pad can assume.
* Keep in mind, that except for the GPIO role you must not assign the same role
* to the more than one pad.
*/
typedef enum {
PAD_MODE_DISABLED = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_REGISTER,
PAD_MODE_CPI0_DATA0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA0,
PAD_MODE_CPI0_DATA1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA1,
PAD_MODE_CPI0_DATA2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA2,
PAD_MODE_CPI0_DATA3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA3,
PAD_MODE_CPI0_DATA4 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA4,
PAD_MODE_CPI0_DATA5 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA5,
PAD_MODE_CPI0_DATA6 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA6,
PAD_MODE_CPI0_DATA7 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA7,
PAD_MODE_CPI0_DATA8 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA8,
PAD_MODE_CPI0_DATA9 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA9,
PAD_MODE_CPI0_HSYNC = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_HSYNC,
PAD_MODE_CPI0_PCLK = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_PCLK,
PAD_MODE_CPI0_VSYNC = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_VSYNC,
PAD_MODE_GPIO = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_GPIO_GPIO00,
PAD_MODE_I2C0_SCL = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2C0_SCL,
PAD_MODE_I2C0_SDA = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2C0_SDA,
PAD_MODE_I2S0_MASTER_SCK = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK,
PAD_MODE_I2S0_MASTER_SD0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0,
PAD_MODE_I2S0_MASTER_SD1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1,
PAD_MODE_I2S0_MASTER_WS = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS,
PAD_MODE_I2S0_SLAVE_SCK = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK,
PAD_MODE_I2S0_SLAVE_SD0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0,
PAD_MODE_I2S0_SLAVE_SD1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1,
PAD_MODE_I2S0_SLAVE_WS = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS,
PAD_MODE_QSPIM0_CSN0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN0,
PAD_MODE_QSPIM0_CSN1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN1,
PAD_MODE_QSPIM0_CSN2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN2,
PAD_MODE_QSPIM0_CSN3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN3,
PAD_MODE_QSPIM0_SCK = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SCK,
PAD_MODE_QSPIM0_SDIO0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0,
PAD_MODE_QSPIM0_SDIO1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1,
PAD_MODE_QSPIM0_SDIO2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2,
PAD_MODE_QSPIM0_SDIO3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3,
PAD_MODE_SDIO0_SDCLK = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDCLK,
PAD_MODE_SDIO0_SDCMD = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDCMD,
PAD_MODE_SDIO0_SDDATA0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0,
PAD_MODE_SDIO0_SDDATA1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1,
PAD_MODE_SDIO0_SDDATA2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2,
PAD_MODE_SDIO0_SDDATA3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3,
PAD_MODE_TIMER0_OUT0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT0,
PAD_MODE_TIMER0_OUT1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT1,
PAD_MODE_TIMER0_OUT2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT2,
PAD_MODE_TIMER0_OUT3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT3,
PAD_MODE_TIMER1_OUT0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT0,
PAD_MODE_TIMER1_OUT1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT1,
PAD_MODE_TIMER1_OUT2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT2,
PAD_MODE_TIMER1_OUT3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT3,
PAD_MODE_TIMER2_OUT0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT0,
PAD_MODE_TIMER2_OUT1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT1,
PAD_MODE_TIMER2_OUT2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT2,
PAD_MODE_TIMER2_OUT3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT3,
PAD_MODE_TIMER3_OUT0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT0,
PAD_MODE_TIMER3_OUT1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT1,
PAD_MODE_TIMER3_OUT2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT2,
PAD_MODE_TIMER3_OUT3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT3,
PAD_MODE_UART0_RX = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_UART0_RX,
PAD_MODE_UART0_TX = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_UART0_TX
} io_mux_mode_e;
typedef enum {
PAD_GPIO00,
PAD_GPIO01,
PAD_GPIO02,
PAD_GPIO03,
PAD_GPIO04,
PAD_GPIO05,
PAD_GPIO06,
PAD_GPIO07,
PAD_GPIO08,
PAD_GPIO09,
PAD_GPIO10,
PAD_GPIO11,
PAD_GPIO12,
PAD_GPIO13,
PAD_GPIO14,
PAD_GPIO15,
PAD_GPIO16,
PAD_GPIO17,
PAD_GPIO18,
PAD_GPIO19,
PAD_GPIO20,
PAD_GPIO21,
PAD_GPIO22,
PAD_GPIO23,
PAD_GPIO24,
PAD_GPIO25,
PAD_GPIO26,
PAD_GPIO27,
PAD_GPIO28,
PAD_GPIO29,
PAD_GPIO30,
PAD_GPIO31,
NUM_PADS
} io_mux_pad_e;
/**
* Change the pad configuration of the given pad
*
* @param pad The pad to configure
* @param cfg [in] The configuration settings for the pad
*/
void io_mux_config_set(io_mux_pad_e pad, io_mux_cfg_t const *cfg);
/**
* Reads the current pad configuration from the pad control peripheral
*
* @param pad The pad from which to read the current configuration
* @param cfg [out] Pointer to the pad config structure where the obtained config will be written to
*/
void io_mux_config_get(io_mux_pad_e pad, io_mux_cfg_t *cfg);
/**
* Change the pad mode (IO multiplex settings)
*
* This function reconfigures the pad multiplexer to route the given IO signal
* to the pad. You must only route the same IO signal to one pad. E.g. you must
* not put PAD_GPIO04 in mode PAD_MODE_I3C0_SCL while PAD_GPIO01 is already in
* the same mode. The only exception to this rule is the PAD_MODE_GPIO. You can
* put all pads into this mode simultaneously to have access to up to NUM_PADS
* GPIOs.
*
* @param pad The pad for which the pad multiplex setting should be changed
*/
void io_mux_mode_set(io_mux_pad_e pad, io_mux_mode_e mode);
/**
* Obtain the current mode of a pad
*
* @param pad The pad for which to return the current pad mode
* @returns The current mode of the pad
*/
io_mux_mode_e io_mux_mode_get(io_mux_pad_e pad);
#endif
#endif /* IO_MUX_H */

4285
drivers/pulpissimo/rtl_sim/io_mux/include/pulpissimo_padframe_all_pads_regs.h Normal file
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drivers/pulpissimo/rtl_sim/io_mux/pulpissimo_padframe_all_pads_regs.hjson Normal file
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56
drivers/pulpissimo/rtl_sim/io_mux/src/io_mux.c Normal file
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@ -0,0 +1,56 @@
/*
* Copyright (C) 2021 ETH Zurich, University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Title: io_mux.c
* Author: Manuel Eggimann <meggimann@iis.ee.ethz.ch>
* Date: 25.08.2021
*
* Description: Implementation for Siracusa's pad control IP driver
*/
#include "io_mux.h"
#include "pulp.h"
void io_mux_config_set(io_mux_pad_e pad, io_mux_cfg_t const *cfg) {
const uint32_t cfg_addr = ARCHI_PAD_CFG_ADDR + pad*IO_MUX_PAD_REG_SEPARATION + IO_MUX_PAD_CFG_REG_OFFSET;
uint32_t reg = pulp_read32(cfg_addr);
reg = bitfield_bit32_write(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_TX_EN_BIT, cfg->tx_en != 0);
reg = bitfield_bit32_write(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_RX_EN_BIT, cfg->rx_en != 0);
reg = bitfield_bit32_write(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_PULL_EN_BIT, cfg->pull_cfg != IO_MUX_NO_PULL);
pulp_write32(cfg_addr, reg);
}
void io_mux_config_get(io_mux_pad_e pad, io_mux_cfg_t *cfg) {
const uint32_t cfg_addr = ARCHI_PAD_CFG_ADDR + pad*IO_MUX_PAD_REG_SEPARATION + IO_MUX_PAD_CFG_REG_OFFSET;
const uint32_t reg = pulp_read32(cfg_addr);
uint8_t pull_en;
cfg->tx_en = bitfield_bit32_read(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_TX_EN_BIT);
cfg->rx_en = bitfield_bit32_read(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_RX_EN_BIT);
pull_en = bitfield_bit32_read(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_PULL_EN_BIT);
cfg->pull_cfg = pull_en? IO_MUX_PULL_EN : IO_MUX_NO_PULL;
}
void io_mux_mode_set(io_mux_pad_e pad, io_mux_mode_e mode) {
const uint32_t cfg_addr = ARCHI_PAD_CFG_ADDR + pad*IO_MUX_PAD_REG_SEPARATION + IO_MUX_PAD_MUX_SEL_REG_OFFSET;
uint32_t reg = pulp_read32(cfg_addr);
reg = bitfield_field32_write(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_FIELD, mode);
pulp_write32(cfg_addr, reg);
}
io_mux_mode_e io_mux_mode_get(io_mux_pad_e pad) {
const uint32_t cfg_addr = ARCHI_PAD_CFG_ADDR + pad*IO_MUX_PAD_REG_SEPARATION + IO_MUX_PAD_MUX_SEL_REG_OFFSET;
const uint32_t reg = pulp_read32(cfg_addr);
return bitfield_field32_read(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_FIELD);
}

2
include/archi/chips/pulpissimo/memory_map.h
View file

@ -49,6 +49,8 @@
#define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET )
#define ARCHI_FC_HWPE_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_HWPE_OFFSET )
#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET )
#define ARCHI_FLL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FLL_OFFSET )
#define ARCHI_PAD_CFG_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_PAD_CFG_OFFSET )

3
include/archi/chips/pulpissimo/pulp.h
View file

@ -44,4 +44,7 @@
#include "archi/udma/uart/udma_uart_v1.h"
#include "archi/udma/udma_v3.h"
#include "gpio.h"
#include "io_mux.h"
#endif

20
include/hal/fll/fll_v1.h
View file

@ -83,22 +83,22 @@ typedef enum {
static inline unsigned int GetFllStatus(int Fll)
{
return (unsigned int) IP_READ((int *) ARCHI_SOC_PERIPHERALS_ADDR, (int) (FLL_STATUS_OFFSET));
return (unsigned int) IP_READ((int *) ARCHI_FLL_ADDR, (int) (FLL_STATUS_OFFSET));
}
static inline unsigned int GetFllConfiguration(int Fll, hal_fll_config_e Reg) {
int Offset = (int) (FLL_CONF1_OFFSET + Reg*4 + Fll*ARCHI_FLL_AREA_SIZE);
return (unsigned int) IP_READ(ARCHI_SOC_PERIPHERALS_ADDR, Offset);
return (unsigned int) IP_READ(ARCHI_FLL_ADDR, Offset);
}
static inline void SetFllConfiguration(int Fll, hal_fll_config_e Reg, unsigned int Value) {
IP_WRITE(ARCHI_SOC_PERIPHERALS_ADDR, FLL_CONF1_OFFSET + Reg*4 + Fll*ARCHI_FLL_AREA_SIZE, Value);
IP_WRITE(ARCHI_FLL_ADDR, FLL_CONF1_OFFSET + Reg*4 + Fll*ARCHI_FLL_AREA_SIZE, Value);
}
static inline unsigned int hal_fll_status_reg_get(int fll)
{
return IP_READ(
ARCHI_SOC_PERIPHERALS_ADDR,
ARCHI_FLL_ADDR,
FLL_STATUS_OFFSET + fll*ARCHI_FLL_AREA_SIZE
);
}
@ -106,7 +106,7 @@ static inline unsigned int hal_fll_status_reg_get(int fll)
static inline void hal_fll_conf_reg1_set(int fll, unsigned int value)
{
IP_WRITE(
ARCHI_SOC_PERIPHERALS_ADDR,
ARCHI_FLL_ADDR,
FLL_CONF1_OFFSET + fll*ARCHI_FLL_AREA_SIZE,
value
);
@ -115,7 +115,7 @@ static inline void hal_fll_conf_reg1_set(int fll, unsigned int value)
static inline unsigned int hal_fll_conf_reg1_get(int fll)
{
return IP_READ(
ARCHI_SOC_PERIPHERALS_ADDR,
ARCHI_FLL_ADDR,
FLL_CONF1_OFFSET + fll*ARCHI_FLL_AREA_SIZE
);
}
@ -123,7 +123,7 @@ static inline unsigned int hal_fll_conf_reg1_get(int fll)
static inline void hal_fll_conf_reg2_set(int fll, unsigned int value)
{
IP_WRITE(
ARCHI_SOC_PERIPHERALS_ADDR,
ARCHI_FLL_ADDR,
FLL_CONF2_OFFSET + fll*ARCHI_FLL_AREA_SIZE,
value
);
@ -132,7 +132,7 @@ static inline void hal_fll_conf_reg2_set(int fll, unsigned int value)
static inline unsigned int hal_fll_conf_reg2_get(int fll)
{
return IP_READ(
ARCHI_SOC_PERIPHERALS_ADDR,
ARCHI_FLL_ADDR,
FLL_CONF2_OFFSET + fll*ARCHI_FLL_AREA_SIZE
);
}
@ -140,7 +140,7 @@ static inline unsigned int hal_fll_conf_reg2_get(int fll)
static inline void hal_fll_integrator_set(int fll, unsigned int value)
{
IP_WRITE(
ARCHI_SOC_PERIPHERALS_ADDR,
ARCHI_FLL_ADDR,
FLL_INTEGRATOR_OFFSET + fll*ARCHI_FLL_AREA_SIZE,
value
);
@ -149,7 +149,7 @@ static inline void hal_fll_integrator_set(int fll, unsigned int value)
static inline unsigned int hal_fll_integrator_get(int fll)
{
return IP_READ(
ARCHI_SOC_PERIPHERALS_ADDR,
ARCHI_FLL_ADDR,
FLL_INTEGRATOR_OFFSET + fll*ARCHI_FLL_AREA_SIZE
);
}

1
include/pulp.h
View file

@ -27,6 +27,7 @@
#include <archi/pulp.h>
#include <hal/pulp.h>
#include <data/data.h>
#include <common/bitfield.h>
typedef enum {
PI_FREQ_DOMAIN_FC = 0,

4
rules/pulp.mk
View file

@ -1 +1,5 @@
ifdef PULPRUN_PLATFORM
platform=$(PULPRUN_PLATFORM)
$(info Setting platform to $(platform))
endif
-include $(PULPRT_HOME)/rules/pulpos/targets/$(PULPRT_TARGET).mk

5
rules/pulpos/default_rules.mk
View file

@ -50,11 +50,6 @@ PULP_APP_CFLAGS += -I$(PULPRT_HOME)/include -I$(PULPRT_HOME)/kernel
PULP_APP_CFLAGS += $(foreach inc,$(PULPOS_MODULES),-I$(inc)/include)
ifdef PULPRUN_PLATFORM
platform=$(PULPRUN_PLATFORM)
endif
override disopt ?= -d
ifeq '$(platform)' 'gvsoc'

9
rules/pulpos/targets/pulpissimo.mk
View file

@ -58,6 +58,15 @@ PULP_SRCS += kernel/fll-v$(fll/version).c
PULP_SRCS += kernel/freq-domains.c
PULP_SRCS += kernel/chips/pulpissimo/soc.c
# GPIO
PULP_SRCS += drivers/gpio/gpio.c
PULP_CFLAGS += -I$(PULPRT_HOME)/drivers/gpio/include
# Pad Multiplexing
ifeq '$(platform)' 'rtl'
PULP_SRCS += drivers/pulpissimo/rtl_sim/io_mux/src/io_mux.c
PULP_CFLAGS += -I$(PULPRT_HOME)/drivers/pulpissimo/rtl_sim/io_mux/include
endif
include $(PULPRT_HOME)/rules/pulpos/configs/default.mk