From baad1c5fff413b8e4443de2b19840e8e1a0f8057 Mon Sep 17 00:00:00 2001 From: Manuel Eggimann Date: Thu, 8 Dec 2022 18:08:21 +0100 Subject: [PATCH] Add new drivers for new gpio and io_mux --- drivers/gpio/gpio.c | 33 +- drivers/gpio/include/gpio.h | 56 +- .../rtl_sim/io_mux/include/io_mux.h | 198 + .../pulpissimo_padframe_all_pads_regs.h | 4285 +++++++++++++++++ .../pulpissimo_padframe_all_pads_regs.hjson | 4091 ++++++++++++++++ .../pulpissimo/rtl_sim/io_mux/src/io_mux.c | 56 + include/archi/chips/pulpissimo/memory_map.h | 2 + include/archi/chips/pulpissimo/pulp.h | 3 + include/hal/fll/fll_v1.h | 20 +- include/pulp.h | 1 + rules/pulp.mk | 4 + rules/pulpos/default_rules.mk | 5 - rules/pulpos/targets/pulpissimo.mk | 9 + 13 files changed, 8722 insertions(+), 41 deletions(-) create mode 100644 drivers/pulpissimo/rtl_sim/io_mux/include/io_mux.h create mode 100644 drivers/pulpissimo/rtl_sim/io_mux/include/pulpissimo_padframe_all_pads_regs.h create mode 100644 drivers/pulpissimo/rtl_sim/io_mux/pulpissimo_padframe_all_pads_regs.hjson create mode 100644 drivers/pulpissimo/rtl_sim/io_mux/src/io_mux.c diff --git a/drivers/gpio/gpio.c b/drivers/gpio/gpio.c index 7cb7aa8..9157945 100644 --- a/drivers/gpio/gpio.c +++ b/drivers/gpio/gpio.c @@ -2,11 +2,17 @@ #include "common/bitfield.h" #include "gpio_hal.h" #include "pulp.h" +#include "hal/utils.h" + +void gpio_init(gpios_t* handle) { + memset(handle, 0, sizeof(gpios_t)); + handle->base_addr = ARCHI_GPIO_ADDR; +} -void gpio_configure(uint32_t number, uint32_t direction){ +void gpio_configure(gpios_t* handle, uint32_t number, uint32_t direction){ // Now configure the GPIO peripheral - uint32_t addr = ARCHI_GPIO_ADDR + GPIO_MODE_REG_OFFSET_BASE + number/16*4; + uint32_t addr = handle->base_addr + GPIO_MODE_REG_OFFSET_BASE + number/16*4; uint32_t reg = archi_read32(addr); bitfield_field32_t field; field.mask = 0x3; @@ -14,28 +20,9 @@ void gpio_configure(uint32_t number, uint32_t direction){ reg = bitfield_field32_write(reg, field, (direction == GPIO_DIRECTION_INPUT)? GPIO_MODE_REG_VALUE_INPUT_ONLY: GPIO_MODE_REG_VALUE_OUTPUT_ACTIVE); archi_write32(addr, reg); // Enable/Disable input sampling - addr = ARCHI_GPIO_ADDR + GPIO_EN_INPUT_REG_OFFSET_BASE + number/32*4; + addr = handle->base_addr + GPIO_EN_INPUT_REG_OFFSET_BASE + number/32*4; reg = archi_read32(addr); - reg = bitfield_bit32_write(reg, number%32, direction == SIRACUSA_GPIO_DIRECTION_INPUT); + reg = bitfield_bit32_write(reg, number%32, direction == GPIO_DIRECTION_INPUT); archi_write32(addr, reg); hal_compiler_barrier(); } - - -void gpio_set(uint32_t number, uint32_t value){ - uint32_t addr; - if (value == 1) { - addr = ARCHI_GPIO_ADDR + GPIO_SET_REG_OFFSET_BASE + number/32*4; - } else { - addr = SIRACUSA_GPIO_BASE_ADDR + GPIO_CLEAR_REG_OFFSET_BASE + number/32*4; - } - archi_write32(addr, 1<<(number%32)); - hal_compiler_barrier(); -} - -uint32_t gpio_get(uint32_t number){ - uint32_t addr = SIRACUSA_GPIO_BASE_ADDR + GPIO_GPIO_IN_0_REG_OFFSET + number/32*4; - uint32_t reg = archi_read32(addr); - return bitfield_bit32_read(reg, number%32); - hal_compiler_barrier(); -} diff --git a/drivers/gpio/include/gpio.h b/drivers/gpio/include/gpio.h index e30ed08..791f63c 100644 --- a/drivers/gpio/include/gpio.h +++ b/drivers/gpio/include/gpio.h @@ -21,13 +21,33 @@ */ #ifndef GPIO_H #define GPIO_H +#ifndef LANGUAGE_ASSEMBLY #include +#include "common/bitfield.h" +#include "gpio_hal.h" +#include "hal/utils.h" +#include "archi/utils.h" + #define GPIO_DIRECTION_OUTPUT 1 #define GPIO_DIRECTION_INPUT 0 +typedef struct { + uint32_t base_addr; +} gpios_t; + +/** + * Initializes the peripheral handle structure + * + * This function must be called before using the handle for gpio interaction. + * + * @param hanlde A pointer to the handle to initialize. + */ +void gpio_init(gpios_t* handle); + + /** * Configure the provided GPIO as either an input or output. * @@ -39,7 +59,7 @@ * @param number The GPIO number to confgiure. You can either use directly an integer number or on of the PAD_GPIOXX macros. * @param direction Either GPIO_DIRECTION_INPUT (0) or GPIO_DIRECTION_OUTPUT */ -void gpio_configure(uint32_t number, uint32_t direction); +void gpio_configure(gpios_t* handle, uint32_t number, uint32_t direction); /** * Get the current value of the GPIO. @@ -49,7 +69,12 @@ void gpio_configure(uint32_t number, uint32_t direction); * @param number The GPIO number to confgiure. You can either use directly an integer number or on of the PAD_GPIOXX macros. * @returns 0 if the gpio is currently at logic level LOW or 1 if it is at logic level HIGH. */ -uint32_t gpio_get(uint32_t number); +static inline uint32_t gpio_get(gpios_t* handle, uint32_t number) { + uint32_t addr = handle->base_addr + GPIO_INPUT_REG_OFFSET_BASE + number/32*4; + uint32_t reg = archi_read32(addr); + return bitfield_bit32_read(reg, number%32); + hal_compiler_barrier(); +} /** * Drive the GPIO to the provided value. @@ -59,6 +84,31 @@ uint32_t gpio_get(uint32_t number); * @param number The GPIO number to confgiure. You can either use directly an integer number or on of the PAD_GPIOXX macros. * @param value Either 0 or 1. */ -void gpio_set(uint32_t number, uint32_t value); +static inline void gpio_set(gpios_t* handle, uint32_t number, uint32_t value) { + uint32_t addr; + if (value == 1) { + addr = handle->base_addr + GPIO_SET_REG_OFFSET_BASE + number/32*4; + } else { + addr = handle->base_addr + GPIO_CLEAR_REG_OFFSET_BASE + number/32*4; + } + archi_write32(addr, 1<<(number%32)); + hal_compiler_barrier(); +} + +/** + * Toggle the GPIO + * + * The corresponding GPIO must have been configured as an output using configure_gpio(). + * + * @param number The GPIO number to confgiure. You can either use directly an integer number or on of the PAD_GPIOXX macros. + */ +static inline void gpio_toggle(gpios_t* handle, uint32_t number) { + uint32_t addr = handle->base_addr + GPIO_TOGGLE_REG_OFFSET_BASE + number/32*4; + archi_write32(addr, 1<<(number%32)); + hal_compiler_barrier(); +} + + +#endif #endif /* GPIO_H */ diff --git a/drivers/pulpissimo/rtl_sim/io_mux/include/io_mux.h b/drivers/pulpissimo/rtl_sim/io_mux/include/io_mux.h new file mode 100644 index 0000000..c716f36 --- /dev/null +++ b/drivers/pulpissimo/rtl_sim/io_mux/include/io_mux.h @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2021 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Title: io_mux.h + * Author: Manuel Eggimann + * Date: 25.08.2021 + * + * Description: Control the pad configuration and multiplexing of the Siracusa chip + */ + +#ifndef IO_MUX_H +#define IO_MUX_H + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "pulpissimo_padframe_all_pads_regs.h" + +#define IO_MUX_PAD_CFG_REG_OFFSET 0x4 +#define IO_MUX_PAD_MUX_SEL_REG_OFFSET 0x8 +#define IO_MUX_PAD_REG_SEPARATION 0x8 + + +typedef enum { + IO_MUX_NO_PULL, ///< No pull resistor is enabled + IO_MUX_PULL_EN, ///< Enable internal pull-up/down (depends on pad kind) resistor +} io_mux_pull_cfg_e; + +/** + * Pad configuration struct + * + * Keep in mind, that certain peripherals might take over control of certain pad + * config signals (e.g. rx_en) if connected to a pad. The settings you provide + * through this API only take effect unless not overriden by the currently + * connected peripheral. + */ +typedef struct { + io_mux_pull_cfg_e pull_cfg; ///< Pull-up/down settings of the pad + uint8_t tx_en; ///< Tx enable + uint8_t rx_en; ///< Rx enable +} io_mux_cfg_t; + +/** + * Pad modes + * + * This enum defines all the different roles a particular IO pad can assume. + * Keep in mind, that except for the GPIO role you must not assign the same role + * to the more than one pad. + */ +typedef enum { + PAD_MODE_DISABLED = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_REGISTER, + PAD_MODE_CPI0_DATA0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA0, + PAD_MODE_CPI0_DATA1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA1, + PAD_MODE_CPI0_DATA2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA2, + PAD_MODE_CPI0_DATA3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA3, + PAD_MODE_CPI0_DATA4 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA4, + PAD_MODE_CPI0_DATA5 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA5, + PAD_MODE_CPI0_DATA6 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA6, + PAD_MODE_CPI0_DATA7 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA7, + PAD_MODE_CPI0_DATA8 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA8, + PAD_MODE_CPI0_DATA9 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA9, + PAD_MODE_CPI0_HSYNC = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_HSYNC, + PAD_MODE_CPI0_PCLK = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_PCLK, + PAD_MODE_CPI0_VSYNC = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_VSYNC, + PAD_MODE_GPIO = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_GPIO_GPIO00, + PAD_MODE_I2C0_SCL = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2C0_SCL, + PAD_MODE_I2C0_SDA = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2C0_SDA, + PAD_MODE_I2S0_MASTER_SCK = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK, + PAD_MODE_I2S0_MASTER_SD0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0, + PAD_MODE_I2S0_MASTER_SD1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1, + PAD_MODE_I2S0_MASTER_WS = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS, + PAD_MODE_I2S0_SLAVE_SCK = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK, + PAD_MODE_I2S0_SLAVE_SD0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0, + PAD_MODE_I2S0_SLAVE_SD1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1, + PAD_MODE_I2S0_SLAVE_WS = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS, + PAD_MODE_QSPIM0_CSN0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN0, + PAD_MODE_QSPIM0_CSN1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN1, + PAD_MODE_QSPIM0_CSN2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN2, + PAD_MODE_QSPIM0_CSN3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN3, + PAD_MODE_QSPIM0_SCK = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SCK, + PAD_MODE_QSPIM0_SDIO0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0, + PAD_MODE_QSPIM0_SDIO1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1, + PAD_MODE_QSPIM0_SDIO2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2, + PAD_MODE_QSPIM0_SDIO3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3, + PAD_MODE_SDIO0_SDCLK = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDCLK, + PAD_MODE_SDIO0_SDCMD = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDCMD, + PAD_MODE_SDIO0_SDDATA0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0, + PAD_MODE_SDIO0_SDDATA1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1, + PAD_MODE_SDIO0_SDDATA2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2, + PAD_MODE_SDIO0_SDDATA3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3, + PAD_MODE_TIMER0_OUT0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT0, + PAD_MODE_TIMER0_OUT1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT1, + PAD_MODE_TIMER0_OUT2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT2, + PAD_MODE_TIMER0_OUT3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT3, + PAD_MODE_TIMER1_OUT0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT0, + PAD_MODE_TIMER1_OUT1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT1, + PAD_MODE_TIMER1_OUT2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT2, + PAD_MODE_TIMER1_OUT3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT3, + PAD_MODE_TIMER2_OUT0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT0, + PAD_MODE_TIMER2_OUT1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT1, + PAD_MODE_TIMER2_OUT2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT2, + PAD_MODE_TIMER2_OUT3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT3, + PAD_MODE_TIMER3_OUT0 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT0, + PAD_MODE_TIMER3_OUT1 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT1, + PAD_MODE_TIMER3_OUT2 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT2, + PAD_MODE_TIMER3_OUT3 = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT3, + PAD_MODE_UART0_RX = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_UART0_RX, + PAD_MODE_UART0_TX = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_UART0_TX +} io_mux_mode_e; + +typedef enum { + PAD_GPIO00, + PAD_GPIO01, + PAD_GPIO02, + PAD_GPIO03, + PAD_GPIO04, + PAD_GPIO05, + PAD_GPIO06, + PAD_GPIO07, + PAD_GPIO08, + PAD_GPIO09, + PAD_GPIO10, + PAD_GPIO11, + PAD_GPIO12, + PAD_GPIO13, + PAD_GPIO14, + PAD_GPIO15, + PAD_GPIO16, + PAD_GPIO17, + PAD_GPIO18, + PAD_GPIO19, + PAD_GPIO20, + PAD_GPIO21, + PAD_GPIO22, + PAD_GPIO23, + PAD_GPIO24, + PAD_GPIO25, + PAD_GPIO26, + PAD_GPIO27, + PAD_GPIO28, + PAD_GPIO29, + PAD_GPIO30, + PAD_GPIO31, + NUM_PADS +} io_mux_pad_e; + +/** + * Change the pad configuration of the given pad + * + * @param pad The pad to configure + * @param cfg [in] The configuration settings for the pad + */ +void io_mux_config_set(io_mux_pad_e pad, io_mux_cfg_t const *cfg); + +/** + * Reads the current pad configuration from the pad control peripheral + * + * @param pad The pad from which to read the current configuration + * @param cfg [out] Pointer to the pad config structure where the obtained config will be written to + */ +void io_mux_config_get(io_mux_pad_e pad, io_mux_cfg_t *cfg); + +/** + * Change the pad mode (IO multiplex settings) + * + * This function reconfigures the pad multiplexer to route the given IO signal + * to the pad. You must only route the same IO signal to one pad. E.g. you must + * not put PAD_GPIO04 in mode PAD_MODE_I3C0_SCL while PAD_GPIO01 is already in + * the same mode. The only exception to this rule is the PAD_MODE_GPIO. You can + * put all pads into this mode simultaneously to have access to up to NUM_PADS + * GPIOs. + * + * @param pad The pad for which the pad multiplex setting should be changed + */ +void io_mux_mode_set(io_mux_pad_e pad, io_mux_mode_e mode); + +/** + * Obtain the current mode of a pad + * + * @param pad The pad for which to return the current pad mode + * @returns The current mode of the pad + */ +io_mux_mode_e io_mux_mode_get(io_mux_pad_e pad); + +#endif +#endif /* IO_MUX_H */ diff --git a/drivers/pulpissimo/rtl_sim/io_mux/include/pulpissimo_padframe_all_pads_regs.h b/drivers/pulpissimo/rtl_sim/io_mux/include/pulpissimo_padframe_all_pads_regs.h new file mode 100644 index 0000000..398806d --- /dev/null +++ b/drivers/pulpissimo/rtl_sim/io_mux/include/pulpissimo_padframe_all_pads_regs.h @@ -0,0 +1,4285 @@ +// Generated register defines for pulpissimo_padframe_all_pads_config + +// Licensing information found in source file: + +#ifndef _PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_REG_DEFS_ +#define _PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_REG_DEFS_ + +#ifdef __cplusplus +extern "C" { +#endif +// Register width +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PARAM_REG_WIDTH 32 + +// Read-only IP Information register +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_REG_OFFSET 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_HW_VERSION_MASK 0xffff +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_HW_VERSION_OFFSET 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_HW_VERSION_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_HW_VERSION_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_HW_VERSION_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_PADCOUNT_MASK 0xffff +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_PADCOUNT_OFFSET 16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_PADCOUNT_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_PADCOUNT_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_PADCOUNT_OFFSET }) + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_REG_OFFSET 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io00. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_REG_OFFSET 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_GPIO_GPIO00 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_REG_OFFSET 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io01. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_REG_OFFSET 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_GPIO_GPIO01 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_REG_OFFSET 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io02. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_REG_OFFSET 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_GPIO_GPIO02 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_REG_OFFSET 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io03. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_REG_OFFSET 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_GPIO_GPIO03 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_REG_OFFSET 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io04. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_REG_OFFSET 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_GPIO_GPIO04 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_REG_OFFSET 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io05. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_REG_OFFSET 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_GPIO_GPIO05 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_REG_OFFSET 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io06. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_REG_OFFSET 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_GPIO_GPIO06 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_REG_OFFSET 0x3c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io07. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_REG_OFFSET 0x40 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_GPIO_GPIO07 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_REG_OFFSET 0x44 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io08. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_REG_OFFSET 0x48 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_GPIO_GPIO08 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_REG_OFFSET 0x4c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io09. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_REG_OFFSET 0x50 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_GPIO_GPIO09 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_REG_OFFSET 0x54 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io10. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_REG_OFFSET 0x58 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_GPIO_GPIO10 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_REG_OFFSET 0x5c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io11. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_REG_OFFSET 0x60 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_GPIO_GPIO11 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_REG_OFFSET 0x64 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io12. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_REG_OFFSET 0x68 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_GPIO_GPIO12 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_REG_OFFSET 0x6c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io13. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_REG_OFFSET 0x70 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_GPIO_GPIO13 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_REG_OFFSET 0x74 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io14. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_REG_OFFSET 0x78 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_GPIO_GPIO14 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_REG_OFFSET 0x7c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io15. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_REG_OFFSET 0x80 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_GPIO_GPIO15 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_REG_OFFSET 0x84 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io16. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_REG_OFFSET 0x88 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_GPIO_GPIO16 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_REG_OFFSET 0x8c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io17. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_REG_OFFSET 0x90 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_GPIO_GPIO17 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_REG_OFFSET 0x94 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io18. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_REG_OFFSET 0x98 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_GPIO_GPIO18 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_REG_OFFSET 0x9c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io19. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_REG_OFFSET 0xa0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_GPIO_GPIO19 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_REG_OFFSET 0xa4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io20. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_REG_OFFSET 0xa8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_GPIO_GPIO20 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_REG_OFFSET 0xac +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io21. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_REG_OFFSET 0xb0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_GPIO_GPIO21 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_REG_OFFSET 0xb4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io22. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_REG_OFFSET 0xb8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_GPIO_GPIO22 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_REG_OFFSET 0xbc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io23. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_REG_OFFSET 0xc0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_GPIO_GPIO23 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_REG_OFFSET 0xc4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io24. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_REG_OFFSET 0xc8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_GPIO_GPIO24 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_REG_OFFSET 0xcc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io25. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_REG_OFFSET 0xd0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_GPIO_GPIO25 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_REG_OFFSET 0xd4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io26. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_REG_OFFSET 0xd8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_GPIO_GPIO26 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_REG_OFFSET 0xdc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io27. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_REG_OFFSET 0xe0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_GPIO_GPIO27 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_REG_OFFSET 0xe4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io28. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_REG_OFFSET 0xe8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_GPIO_GPIO28 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_REG_OFFSET 0xec +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io29. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_REG_OFFSET 0xf0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_GPIO_GPIO29 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_REG_OFFSET 0xf4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io30. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_REG_OFFSET 0xf8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_GPIO_GPIO30 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +// Pad signal configuration. +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_REG_OFFSET 0xfc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_CHIP2PAD_BIT 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_PULL_EN_BIT 1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_RX_EN_BIT 2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_TX_EN_BIT 3 + +// Pad signal port multiplex selection for pad pad_io31. The programmed value +// defines which port +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_REG_OFFSET 0x100 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_MASK \ + 0x3f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_OFFSET \ + 0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_OFFSET }) +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA0 \ + 0x1 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA1 \ + 0x2 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA2 \ + 0x3 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA3 \ + 0x4 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA4 \ + 0x5 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA5 \ + 0x6 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA6 \ + 0x7 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA7 \ + 0x8 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA8 \ + 0x9 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA9 \ + 0xa +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_HSYNC \ + 0xb +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_PCLK \ + 0xc +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_VSYNC \ + 0xd +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_GPIO_GPIO31 \ + 0xe +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2C0_SCL \ + 0xf +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2C0_SDA \ + 0x10 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \ + 0x11 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \ + 0x12 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \ + 0x13 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \ + 0x14 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \ + 0x15 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \ + 0x16 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \ + 0x17 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \ + 0x18 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \ + 0x19 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \ + 0x1a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \ + 0x1b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \ + 0x1c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_SCK \ + 0x1d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \ + 0x1e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \ + 0x1f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \ + 0x20 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \ + 0x21 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \ + 0x22 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \ + 0x23 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \ + 0x24 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \ + 0x25 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \ + 0x26 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \ + 0x27 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \ + 0x28 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \ + 0x29 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \ + 0x2a +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \ + 0x2b +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \ + 0x2c +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \ + 0x2d +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \ + 0x2e +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \ + 0x2f +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \ + 0x30 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \ + 0x31 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \ + 0x32 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \ + 0x33 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \ + 0x34 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \ + 0x35 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \ + 0x36 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \ + 0x37 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_UART0_RX \ + 0x38 +#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_UART0_TX \ + 0x39 + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_REG_DEFS_ +// End generated register defines for pulpissimo_padframe_all_pads_config \ No newline at end of file diff --git a/drivers/pulpissimo/rtl_sim/io_mux/pulpissimo_padframe_all_pads_regs.hjson b/drivers/pulpissimo/rtl_sim/io_mux/pulpissimo_padframe_all_pads_regs.hjson new file mode 100644 index 0000000..634d435 --- /dev/null +++ b/drivers/pulpissimo/rtl_sim/io_mux/pulpissimo_padframe_all_pads_regs.hjson @@ -0,0 +1,4091 @@ + + +{ + # File auto-generated by Padrick unknown + name: "pulpissimo_padframe_all_pads_config" + clock_primary: "clk_i" + reset_primary: "rst_ni" + bus_interfaces: [ + { protocol: "reg_iface", direction: "device"} + ] + regwidth: 32, + registers: [ + {skipto: "0x0"}, + { + name: INFO + desc: "Read-only IP Information register" + swaccess: "ro" + hwaccess: "hro" + fields: [ + { + bits: "15:0" + name: HW_VERSION + desc: "Hardware version ID." + resval: 2 + }, + { + bits:"31:16" + name: PADCOUNT + desc: "The number of muxable pads in this IP." + resval: "32" + } + ] + } + + + + + + + + + + + + + + + + + + + + + + + + + { + name: PAD_IO00_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO00_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io00. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio00", desc: "Connect port gpio00 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO01_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO01_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io01. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio01", desc: "Connect port gpio01 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO02_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO02_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io02. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio02", desc: "Connect port gpio02 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO03_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO03_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io03. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio03", desc: "Connect port gpio03 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO04_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO04_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io04. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio04", desc: "Connect port gpio04 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO05_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO05_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io05. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio05", desc: "Connect port gpio05 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO06_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO06_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io06. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio06", desc: "Connect port gpio06 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO07_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO07_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io07. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio07", desc: "Connect port gpio07 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO08_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO08_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io08. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio08", desc: "Connect port gpio08 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO09_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO09_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io09. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio09", desc: "Connect port gpio09 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO10_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO10_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io10. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio10", desc: "Connect port gpio10 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO11_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO11_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io11. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio11", desc: "Connect port gpio11 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO12_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO12_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io12. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio12", desc: "Connect port gpio12 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO13_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO13_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io13. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio13", desc: "Connect port gpio13 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO14_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO14_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io14. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio14", desc: "Connect port gpio14 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO15_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO15_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io15. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio15", desc: "Connect port gpio15 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO16_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO16_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io16. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio16", desc: "Connect port gpio16 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO17_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO17_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io17. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio17", desc: "Connect port gpio17 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO18_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO18_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io18. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio18", desc: "Connect port gpio18 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO19_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO19_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io19. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio19", desc: "Connect port gpio19 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO20_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO20_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io20. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio20", desc: "Connect port gpio20 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO21_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO21_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io21. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio21", desc: "Connect port gpio21 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO22_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO22_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io22. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio22", desc: "Connect port gpio22 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO23_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO23_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io23. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio23", desc: "Connect port gpio23 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO24_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO24_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io24. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio24", desc: "Connect port gpio24 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO25_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO25_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io25. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio25", desc: "Connect port gpio25 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO26_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO26_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io26. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio26", desc: "Connect port gpio26 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO27_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO27_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io27. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio27", desc: "Connect port gpio27 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO28_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO28_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io28. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio28", desc: "Connect port gpio28 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO29_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO29_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io29. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio29", desc: "Connect port gpio29 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO30_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO30_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io30. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio30", desc: "Connect port gpio30 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + { + name: PAD_IO31_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Connects to pad's TX driver + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: pull_en + desc: ''' + Enable pull up/down (depends on the selected IO pad) resistor, active-high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: rx_en + desc: ''' + RX enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "1" + }, + { + bits: "3" + name: tx_en + desc: ''' + TX driver enable, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO31_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io31. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 14 + fields: [ + { + bits: "5:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_cpi0_data0", desc: "Connect port data0 from port group cpi0 to this pad." } + { value: "2", name: "port_cpi0_data1", desc: "Connect port data1 from port group cpi0 to this pad." } + { value: "3", name: "port_cpi0_data2", desc: "Connect port data2 from port group cpi0 to this pad." } + { value: "4", name: "port_cpi0_data3", desc: "Connect port data3 from port group cpi0 to this pad." } + { value: "5", name: "port_cpi0_data4", desc: "Connect port data4 from port group cpi0 to this pad." } + { value: "6", name: "port_cpi0_data5", desc: "Connect port data5 from port group cpi0 to this pad." } + { value: "7", name: "port_cpi0_data6", desc: "Connect port data6 from port group cpi0 to this pad." } + { value: "8", name: "port_cpi0_data7", desc: "Connect port data7 from port group cpi0 to this pad." } + { value: "9", name: "port_cpi0_data8", desc: "Connect port data8 from port group cpi0 to this pad." } + { value: "10", name: "port_cpi0_data9", desc: "Connect port data9 from port group cpi0 to this pad." } + { value: "11", name: "port_cpi0_hsync", desc: "Connect port hsync from port group cpi0 to this pad." } + { value: "12", name: "port_cpi0_pclk", desc: "Connect port pclk from port group cpi0 to this pad." } + { value: "13", name: "port_cpi0_vsync", desc: "Connect port vsync from port group cpi0 to this pad." } + { value: "14", name: "port_gpio_gpio31", desc: "Connect port gpio31 from port group gpio to this pad." } + { value: "15", name: "port_i2c0_scl", desc: "Connect port scl from port group i2c0 to this pad." } + { value: "16", name: "port_i2c0_sda", desc: "Connect port sda from port group i2c0 to this pad." } + { value: "17", name: "port_i2s0_master_sck", desc: "Connect port master_sck from port group i2s0 to this pad." } + { value: "18", name: "port_i2s0_master_sd0", desc: "Connect port master_sd0 from port group i2s0 to this pad." } + { value: "19", name: "port_i2s0_master_sd1", desc: "Connect port master_sd1 from port group i2s0 to this pad." } + { value: "20", name: "port_i2s0_master_ws", desc: "Connect port master_ws from port group i2s0 to this pad." } + { value: "21", name: "port_i2s0_slave_sck", desc: "Connect port slave_sck from port group i2s0 to this pad." } + { value: "22", name: "port_i2s0_slave_sd0", desc: "Connect port slave_sd0 from port group i2s0 to this pad." } + { value: "23", name: "port_i2s0_slave_sd1", desc: "Connect port slave_sd1 from port group i2s0 to this pad." } + { value: "24", name: "port_i2s0_slave_ws", desc: "Connect port slave_ws from port group i2s0 to this pad." } + { value: "25", name: "port_qspim0_csn0", desc: "Connect port csn0 from port group qspim0 to this pad." } + { value: "26", name: "port_qspim0_csn1", desc: "Connect port csn1 from port group qspim0 to this pad." } + { value: "27", name: "port_qspim0_csn2", desc: "Connect port csn2 from port group qspim0 to this pad." } + { value: "28", name: "port_qspim0_csn3", desc: "Connect port csn3 from port group qspim0 to this pad." } + { value: "29", name: "port_qspim0_sck", desc: "Connect port sck from port group qspim0 to this pad." } + { value: "30", name: "port_qspim0_sdio0", desc: "Connect port sdio0 from port group qspim0 to this pad." } + { value: "31", name: "port_qspim0_sdio1", desc: "Connect port sdio1 from port group qspim0 to this pad." } + { value: "32", name: "port_qspim0_sdio2", desc: "Connect port sdio2 from port group qspim0 to this pad." } + { value: "33", name: "port_qspim0_sdio3", desc: "Connect port sdio3 from port group qspim0 to this pad." } + { value: "34", name: "port_sdio0_sdclk", desc: "Connect port sdclk from port group sdio0 to this pad." } + { value: "35", name: "port_sdio0_sdcmd", desc: "Connect port sdcmd from port group sdio0 to this pad." } + { value: "36", name: "port_sdio0_sddata0", desc: "Connect port sddata0 from port group sdio0 to this pad." } + { value: "37", name: "port_sdio0_sddata1", desc: "Connect port sddata1 from port group sdio0 to this pad." } + { value: "38", name: "port_sdio0_sddata2", desc: "Connect port sddata2 from port group sdio0 to this pad." } + { value: "39", name: "port_sdio0_sddata3", desc: "Connect port sddata3 from port group sdio0 to this pad." } + { value: "40", name: "port_timer0_out0", desc: "Connect port out0 from port group timer0 to this pad." } + { value: "41", name: "port_timer0_out1", desc: "Connect port out1 from port group timer0 to this pad." } + { value: "42", name: "port_timer0_out2", desc: "Connect port out2 from port group timer0 to this pad." } + { value: "43", name: "port_timer0_out3", desc: "Connect port out3 from port group timer0 to this pad." } + { value: "44", name: "port_timer1_out0", desc: "Connect port out0 from port group timer1 to this pad." } + { value: "45", name: "port_timer1_out1", desc: "Connect port out1 from port group timer1 to this pad." } + { value: "46", name: "port_timer1_out2", desc: "Connect port out2 from port group timer1 to this pad." } + { value: "47", name: "port_timer1_out3", desc: "Connect port out3 from port group timer1 to this pad." } + { value: "48", name: "port_timer2_out0", desc: "Connect port out0 from port group timer2 to this pad." } + { value: "49", name: "port_timer2_out1", desc: "Connect port out1 from port group timer2 to this pad." } + { value: "50", name: "port_timer2_out2", desc: "Connect port out2 from port group timer2 to this pad." } + { value: "51", name: "port_timer2_out3", desc: "Connect port out3 from port group timer2 to this pad." } + { value: "52", name: "port_timer3_out0", desc: "Connect port out0 from port group timer3 to this pad." } + { value: "53", name: "port_timer3_out1", desc: "Connect port out1 from port group timer3 to this pad." } + { value: "54", name: "port_timer3_out2", desc: "Connect port out2 from port group timer3 to this pad." } + { value: "55", name: "port_timer3_out3", desc: "Connect port out3 from port group timer3 to this pad." } + { value: "56", name: "port_uart0_rx", desc: "Connect port rx from port group uart0 to this pad." } + { value: "57", name: "port_uart0_tx", desc: "Connect port tx from port group uart0 to this pad." } + ] + } + ] + } + + ] +} diff --git a/drivers/pulpissimo/rtl_sim/io_mux/src/io_mux.c b/drivers/pulpissimo/rtl_sim/io_mux/src/io_mux.c new file mode 100644 index 0000000..543dfe8 --- /dev/null +++ b/drivers/pulpissimo/rtl_sim/io_mux/src/io_mux.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2021 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Title: io_mux.c + * Author: Manuel Eggimann + * Date: 25.08.2021 + * + * Description: Implementation for Siracusa's pad control IP driver + */ + +#include "io_mux.h" +#include "pulp.h" + +void io_mux_config_set(io_mux_pad_e pad, io_mux_cfg_t const *cfg) { + const uint32_t cfg_addr = ARCHI_PAD_CFG_ADDR + pad*IO_MUX_PAD_REG_SEPARATION + IO_MUX_PAD_CFG_REG_OFFSET; + uint32_t reg = pulp_read32(cfg_addr); + reg = bitfield_bit32_write(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_TX_EN_BIT, cfg->tx_en != 0); + reg = bitfield_bit32_write(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_RX_EN_BIT, cfg->rx_en != 0); + reg = bitfield_bit32_write(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_PULL_EN_BIT, cfg->pull_cfg != IO_MUX_NO_PULL); + pulp_write32(cfg_addr, reg); +} + +void io_mux_config_get(io_mux_pad_e pad, io_mux_cfg_t *cfg) { + const uint32_t cfg_addr = ARCHI_PAD_CFG_ADDR + pad*IO_MUX_PAD_REG_SEPARATION + IO_MUX_PAD_CFG_REG_OFFSET; + const uint32_t reg = pulp_read32(cfg_addr); + uint8_t pull_en; + cfg->tx_en = bitfield_bit32_read(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_TX_EN_BIT); + cfg->rx_en = bitfield_bit32_read(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_RX_EN_BIT); + pull_en = bitfield_bit32_read(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_PULL_EN_BIT); + cfg->pull_cfg = pull_en? IO_MUX_PULL_EN : IO_MUX_NO_PULL; +} + +void io_mux_mode_set(io_mux_pad_e pad, io_mux_mode_e mode) { + const uint32_t cfg_addr = ARCHI_PAD_CFG_ADDR + pad*IO_MUX_PAD_REG_SEPARATION + IO_MUX_PAD_MUX_SEL_REG_OFFSET; + uint32_t reg = pulp_read32(cfg_addr); + reg = bitfield_field32_write(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_FIELD, mode); + pulp_write32(cfg_addr, reg); +} + +io_mux_mode_e io_mux_mode_get(io_mux_pad_e pad) { + const uint32_t cfg_addr = ARCHI_PAD_CFG_ADDR + pad*IO_MUX_PAD_REG_SEPARATION + IO_MUX_PAD_MUX_SEL_REG_OFFSET; + const uint32_t reg = pulp_read32(cfg_addr); + return bitfield_field32_read(reg, PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_FIELD); +} diff --git a/include/archi/chips/pulpissimo/memory_map.h b/include/archi/chips/pulpissimo/memory_map.h index 8425b4b..8e8314d 100644 --- a/include/archi/chips/pulpissimo/memory_map.h +++ b/include/archi/chips/pulpissimo/memory_map.h @@ -49,6 +49,8 @@ #define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) #define ARCHI_FC_HWPE_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_HWPE_OFFSET ) #define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) +#define ARCHI_FLL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FLL_OFFSET ) +#define ARCHI_PAD_CFG_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_PAD_CFG_OFFSET ) diff --git a/include/archi/chips/pulpissimo/pulp.h b/include/archi/chips/pulpissimo/pulp.h index 7c3eaea..f07fbc7 100644 --- a/include/archi/chips/pulpissimo/pulp.h +++ b/include/archi/chips/pulpissimo/pulp.h @@ -44,4 +44,7 @@ #include "archi/udma/uart/udma_uart_v1.h" #include "archi/udma/udma_v3.h" +#include "gpio.h" +#include "io_mux.h" + #endif diff --git a/include/hal/fll/fll_v1.h b/include/hal/fll/fll_v1.h index 16574d9..c608d99 100644 --- a/include/hal/fll/fll_v1.h +++ b/include/hal/fll/fll_v1.h @@ -83,22 +83,22 @@ typedef enum { static inline unsigned int GetFllStatus(int Fll) { - return (unsigned int) IP_READ((int *) ARCHI_SOC_PERIPHERALS_ADDR, (int) (FLL_STATUS_OFFSET)); + return (unsigned int) IP_READ((int *) ARCHI_FLL_ADDR, (int) (FLL_STATUS_OFFSET)); } static inline unsigned int GetFllConfiguration(int Fll, hal_fll_config_e Reg) { int Offset = (int) (FLL_CONF1_OFFSET + Reg*4 + Fll*ARCHI_FLL_AREA_SIZE); - return (unsigned int) IP_READ(ARCHI_SOC_PERIPHERALS_ADDR, Offset); + return (unsigned int) IP_READ(ARCHI_FLL_ADDR, Offset); } static inline void SetFllConfiguration(int Fll, hal_fll_config_e Reg, unsigned int Value) { - IP_WRITE(ARCHI_SOC_PERIPHERALS_ADDR, FLL_CONF1_OFFSET + Reg*4 + Fll*ARCHI_FLL_AREA_SIZE, Value); + IP_WRITE(ARCHI_FLL_ADDR, FLL_CONF1_OFFSET + Reg*4 + Fll*ARCHI_FLL_AREA_SIZE, Value); } static inline unsigned int hal_fll_status_reg_get(int fll) { return IP_READ( - ARCHI_SOC_PERIPHERALS_ADDR, + ARCHI_FLL_ADDR, FLL_STATUS_OFFSET + fll*ARCHI_FLL_AREA_SIZE ); } @@ -106,7 +106,7 @@ static inline unsigned int hal_fll_status_reg_get(int fll) static inline void hal_fll_conf_reg1_set(int fll, unsigned int value) { IP_WRITE( - ARCHI_SOC_PERIPHERALS_ADDR, + ARCHI_FLL_ADDR, FLL_CONF1_OFFSET + fll*ARCHI_FLL_AREA_SIZE, value ); @@ -115,7 +115,7 @@ static inline void hal_fll_conf_reg1_set(int fll, unsigned int value) static inline unsigned int hal_fll_conf_reg1_get(int fll) { return IP_READ( - ARCHI_SOC_PERIPHERALS_ADDR, + ARCHI_FLL_ADDR, FLL_CONF1_OFFSET + fll*ARCHI_FLL_AREA_SIZE ); } @@ -123,7 +123,7 @@ static inline unsigned int hal_fll_conf_reg1_get(int fll) static inline void hal_fll_conf_reg2_set(int fll, unsigned int value) { IP_WRITE( - ARCHI_SOC_PERIPHERALS_ADDR, + ARCHI_FLL_ADDR, FLL_CONF2_OFFSET + fll*ARCHI_FLL_AREA_SIZE, value ); @@ -132,7 +132,7 @@ static inline void hal_fll_conf_reg2_set(int fll, unsigned int value) static inline unsigned int hal_fll_conf_reg2_get(int fll) { return IP_READ( - ARCHI_SOC_PERIPHERALS_ADDR, + ARCHI_FLL_ADDR, FLL_CONF2_OFFSET + fll*ARCHI_FLL_AREA_SIZE ); } @@ -140,7 +140,7 @@ static inline unsigned int hal_fll_conf_reg2_get(int fll) static inline void hal_fll_integrator_set(int fll, unsigned int value) { IP_WRITE( - ARCHI_SOC_PERIPHERALS_ADDR, + ARCHI_FLL_ADDR, FLL_INTEGRATOR_OFFSET + fll*ARCHI_FLL_AREA_SIZE, value ); @@ -149,7 +149,7 @@ static inline void hal_fll_integrator_set(int fll, unsigned int value) static inline unsigned int hal_fll_integrator_get(int fll) { return IP_READ( - ARCHI_SOC_PERIPHERALS_ADDR, + ARCHI_FLL_ADDR, FLL_INTEGRATOR_OFFSET + fll*ARCHI_FLL_AREA_SIZE ); } diff --git a/include/pulp.h b/include/pulp.h index c56b2d5..6e10f84 100755 --- a/include/pulp.h +++ b/include/pulp.h @@ -27,6 +27,7 @@ #include #include #include +#include typedef enum { PI_FREQ_DOMAIN_FC = 0, diff --git a/rules/pulp.mk b/rules/pulp.mk index 92b989e..64daf40 100644 --- a/rules/pulp.mk +++ b/rules/pulp.mk @@ -1 +1,5 @@ +ifdef PULPRUN_PLATFORM +platform=$(PULPRUN_PLATFORM) +$(info Setting platform to $(platform)) +endif -include $(PULPRT_HOME)/rules/pulpos/targets/$(PULPRT_TARGET).mk diff --git a/rules/pulpos/default_rules.mk b/rules/pulpos/default_rules.mk index c710574..bfe60b2 100644 --- a/rules/pulpos/default_rules.mk +++ b/rules/pulpos/default_rules.mk @@ -50,11 +50,6 @@ PULP_APP_CFLAGS += -I$(PULPRT_HOME)/include -I$(PULPRT_HOME)/kernel PULP_APP_CFLAGS += $(foreach inc,$(PULPOS_MODULES),-I$(inc)/include) -ifdef PULPRUN_PLATFORM -platform=$(PULPRUN_PLATFORM) -endif - - override disopt ?= -d ifeq '$(platform)' 'gvsoc' diff --git a/rules/pulpos/targets/pulpissimo.mk b/rules/pulpos/targets/pulpissimo.mk index 79492b0..9026586 100644 --- a/rules/pulpos/targets/pulpissimo.mk +++ b/rules/pulpos/targets/pulpissimo.mk @@ -58,6 +58,15 @@ PULP_SRCS += kernel/fll-v$(fll/version).c PULP_SRCS += kernel/freq-domains.c PULP_SRCS += kernel/chips/pulpissimo/soc.c +# GPIO +PULP_SRCS += drivers/gpio/gpio.c +PULP_CFLAGS += -I$(PULPRT_HOME)/drivers/gpio/include + +# Pad Multiplexing +ifeq '$(platform)' 'rtl' +PULP_SRCS += drivers/pulpissimo/rtl_sim/io_mux/src/io_mux.c +PULP_CFLAGS += -I$(PULPRT_HOME)/drivers/pulpissimo/rtl_sim/io_mux/include +endif include $(PULPRT_HOME)/rules/pulpos/configs/default.mk