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Add sync loop barrier with proper address

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This commit is contained in:
Riccardo Tedeschi 2023-10-25 09:46:54 +02:00
parent 8e7c7bf55b
commit 28b2b3638a
1 changed files with 5 additions and 0 deletions
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5
kernel/crt0.S
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@ -30,6 +30,8 @@ pos_init_entry:
# PEs from 1 to 7 will go to sync_loop and wait. PE0 will reach them
# later after the pos_init_start. Then, they'll set up their stack into
# the L1 and jump to cluster_entry_stub
li t0, 0x10000000
sw x0, 0(t0)
bnez a0, sync_loop
#else
srli a0, a0, 5
@ -74,6 +76,9 @@ pos_init_entry:
#ifdef ARCHI_NO_FC
csrr a0, 0xF14
andi a1, a0, 0x1f
li t0, 0x10000000
li t1, 0x1
sw t1, 0(t0)
j pe_start
#endif