From 28b2b3638a10fd908fbc258784c7a13df31a975a Mon Sep 17 00:00:00 2001
From: Riccardo Tedeschi <riccardo.tedeschi4@studio.unibo.it>
Date: Wed, 25 Oct 2023 09:46:54 +0200
Subject: [PATCH] Add sync loop barrier with proper address

---
 kernel/crt0.S | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/kernel/crt0.S b/kernel/crt0.S
index d2dc482..6a39dfd 100644
--- a/kernel/crt0.S
+++ b/kernel/crt0.S
@@ -30,6 +30,8 @@ pos_init_entry:
     # PEs from 1 to 7 will go to sync_loop and wait. PE0 will reach them
     # later after the pos_init_start. Then, they'll set up their stack into
     # the L1 and jump to cluster_entry_stub
+    li t0, 0x10000000
+    sw x0, 0(t0)
     bnez    a0,  sync_loop
 #else   
     srli    a0, a0, 5
@@ -74,6 +76,9 @@ pos_init_entry:
 #ifdef ARCHI_NO_FC
     csrr    a0, 0xF14
     andi    a1, a0, 0x1f
+    li t0, 0x10000000
+    li t1, 0x1
+    sw t1, 0(t0)
     j pe_start
 #endif