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Few fixes to have riscv-tests/testIRQ working on pulpissimo

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This commit is contained in:
Germain Haugou 2020-02-06 13:26:14 +01:00
parent ea1c172836
commit 0540056eaa
9 changed files with 44 additions and 17 deletions
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1
include/archi/chips/marsellus/properties.h
View file

@ -98,6 +98,7 @@
#define ARCHI_FC_CID 31
#define ARCHI_HAS_FC_ITC 1
#define ARCHI_HAS_FC 1
#define ARCHI_CORE_HAS_1_10 1
/*

1
include/archi/chips/pulp/properties.h
View file

@ -99,6 +99,7 @@
#define ARCHI_FC_CID 31
#define ARCHI_HAS_FC_ITC 1
#define ARCHI_HAS_FC 1
#define ARCHI_CORE_HAS_1_10 1
#endif

1
include/archi/chips/pulpissimo/properties.h
View file

@ -78,6 +78,7 @@
#define ARCHI_FC_CID 31
#define ARCHI_HAS_FC_ITC 1
#define ARCHI_HAS_FC 1
#define ARCHI_CORE_HAS_1_10 1

8
include/hal/timer/timer_v2.h
View file

@ -42,6 +42,14 @@ static inline unsigned int timer_base_cl(int cid, int id, int sub_id)
return ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_TIMER_OFFSET + id * ARCHI_TIMER_SIZE + sub_id * 4;
}
#else
static inline unsigned int timer_base_cl(int cid, int id, int sub_id)
{
return 0;
}
#endif

14
include/implem/irq.h
View file

@ -23,11 +23,11 @@
void pos_irq_init();
void pos_irq_set_handler(int irq, void (*handler)());
void rt_irq_set_handler(int irq, void (*handler)());
static inline void pos_irq_mask_set(unsigned int mask)
static inline void rt_irq_mask_set(unsigned int mask)
{
#if defined(__RISCV_GENERIC__)
// Generic riscv case, e.g. Ibex
@ -58,7 +58,7 @@ static inline void pos_irq_mask_set(unsigned int mask)
static inline void pos_irq_mask_clr(unsigned int mask)
static inline void rt_irq_mask_clr(unsigned int mask)
{
#if defined(__RISCV_GENERIC__)
hal_spr_read_then_clr_from_reg(0x304, mask);
@ -82,7 +82,7 @@ static inline void pos_irq_mask_clr(unsigned int mask)
static inline void pos_irq_clr(unsigned int mask)
static inline void rt_irq_clr(unsigned int mask)
{
#if defined(__RISCV_GENERIC__)
// TODO
@ -101,7 +101,7 @@ static inline void pos_irq_clr(unsigned int mask)
#endif
}
static inline unsigned int pos_irq_get_fc_vector_base()
static inline unsigned int rt_irq_get_fc_vector_base()
{
if (hal_is_fc())
{
@ -129,7 +129,7 @@ static inline unsigned int pos_irq_get_fc_vector_base()
static inline void pos_irq_set_fc_vector_base(unsigned int base)
static inline void rt_irq_set_fc_vector_base(unsigned int base)
{
if (hal_is_fc())
{
@ -154,7 +154,7 @@ static inline void pos_irq_set_fc_vector_base(unsigned int base)
}
static inline void pos_irq_wait_for_interrupt()
static inline void rt_irq_wait_for_interrupt()
{
#if !defined(ARCHI_HAS_FC) || defined(ARCHI_HAS_FC_EU)
eu_evt_wait();

15
include/pulp.h
View file

@ -34,12 +34,27 @@ typedef enum {
PI_FREQ_DOMAIN_PERIPH = 2
} pi_freq_domain_e;
#ifdef ARCHI_HAS_CLUSTER
void cluster_start(int cid, int (*entry)());
void cluster_entry_stub();
int cluster_wait(int cid);
#else
static inline void cluster_start(int cid, int (*entry)())
{
}
static inline int cluster_wait(int cid)
{
return 0;
}
#endif
void _start();
#include <implem/implem.h>

4
kernel/crt0.S
View file

@ -89,7 +89,7 @@ pos_init_entry:
#ifdef ARCHI_CORE_HAS_1_10
j pos_illegal_instr
j __rt_handle_illegal_instr
#else
j pos_no_irq_handler
#endif
@ -134,7 +134,7 @@ _start:
pos_illegal_instr:
j pos_irq_illegal_instr
j __rt_handle_illegal_instr
pos_no_irq_handler:
mret

6
kernel/fll-v1.c
View file

@ -98,9 +98,9 @@ void pos_freq_wait_convergence(int fll)
if ( mult_factor_diff <= tolerance)
break;
pos_irq_mask_set(1<<ARCHI_FC_EVT_CLK_REF);
pos_irq_wait_for_interrupt();
pos_irq_mask_clr(1<<ARCHI_FC_EVT_CLK_REF);
rt_irq_mask_set(1<<ARCHI_FC_EVT_CLK_REF);
rt_irq_wait_for_interrupt();
rt_irq_mask_clr(1<<ARCHI_FC_EVT_CLK_REF);
} while (1);
hal_irq_restore(irq);

11
kernel/irq.c
View file

@ -43,7 +43,7 @@ static unsigned int pos_irq_get_itvec(unsigned int ItBaseAddr, unsigned int ItIn
void pos_irq_set_handler(int irq, void (*handler)())
void rt_irq_set_handler(int irq, void (*handler)())
{
#if defined(__RISCV_GENERIC__)
if (irq < 16)
@ -52,7 +52,7 @@ void pos_irq_set_handler(int irq, void (*handler)())
irq -= 16;
#endif
unsigned int base = pos_irq_get_fc_vector_base();
unsigned int base = rt_irq_get_fc_vector_base();
unsigned int jmpAddr = base + 0x4 * irq;
@ -70,7 +70,7 @@ void pos_irq_set_handler(int irq, void (*handler)())
void pos_irq_illegal_instr()
void __rt_handle_illegal_instr()
{
//unsigned int mepc = hal_mepc_read();
//rt_warning("Reached illegal instruction (PC: 0x%x, opcode: 0x%x\n", mepc, *(int *)mepc);
@ -83,9 +83,10 @@ void pos_irq_init()
{
// We may enter the runtime with some interrupts active for example
// if we force the boot to jump to the runtime through jtag.
pos_irq_mask_clr(-1);
rt_irq_mask_clr(-1);
// As the FC code may not be at the beginning of the L2, set the
// vector base to get proper interrupt handlers
pos_irq_set_fc_vector_base(pos_irq_vector_base());
rt_irq_set_fc_vector_base(pos_irq_vector_base());
}