Add runtime optimization support to ONNX -> ORT format conversion script.
Replace `--optimization_level`, `--use_nnapi`, and `--use_coreml` with a new `--optimization_style` option.
* creating a test for printing ort tensor
* modifying comment for error case
* Using Output Grabber to assert the print output
* modifying the print ort test
* removing comments
* removing sys import
* Use numpy.percentile to get the lookup value.
* Use 1.0 as float value rather than integer.
* Add missing cdf parameter for `np.percentile`.
* Use 100. instead of 1.0
* Remove print.
* Update from @yufenglee
* Add support for opset 16 to transpose optimizer.
Only change required is for GridSample to be added to the layout sensitive ops. The existing handling for layout transpose works with that as the first input and first output are layout sensitive.
Update the optimize to be able to return an error message if it fails.
This PR is just for making onnxruntime passing Binskim rules.
Below is how I made it:
git clone absl repo, checkout the version we are using
Then apply our patch file
Make modifications
Regenerate the patch file by "git diff > C:\src\onnxruntime\cmake\patch\xxx.patch"
Then submit the change to our repo
You will need to repeat the steps when you need to advance the absl commit or add more changes to it.
When returning by value in a cross DLL call, the hash table
even though containing all the entries that are originally there
can not find at least some of them. Reverting to std::unordered_set
pending further investigation.
* Add micro-benchmarks for Attention and SkipLayerNormalization ops.
* Add choices for argument provider and precision.
* Automatically select CUDA or ROCM execution provider.
Current training optimizer kernels include CPU headers
that affects changes that we can make in the CPU code with C++14 compiler and
other refactoring efforts. Rearrange the kernel according to the established patterns
and do not include headers that are not needed.
ARM a55 micro-architecture (with dot product instructions), similar to a53, is widely used as little cores in big.Little configurations. A55 has a narrower memory load/store hardware, where a 128b load instruction would block the pipeline for 2 whole cycles, during which no other instructions can be executed. On the other hand, a 64b load instruction can be duo issued with many other instructions.
This change adds a Symmetric QGEMM kernel for a55 micro-architecture, where we replace
ldr q4,[x1],#16
with
ldr d4,[x1],#8
ldr x11,[x1],#8
ins v4.d[1],x11
so that we can try to hide the memory load cycles behind computing cycles in the kernel.
Co-authored-by: Chen Fu <fuchen@microsoft.com>
