07bf3478fa
This code was originally in https://github.com/betrusted-io/rom-locate. However, the majority of that crate is concerned with creating the database files necessary for the patching, and it pulls in a lot of dependencies. Changing hardware targets is considered to be a "huge" change for this project, so we're pushing the code generator directly into xous-core, and commiting the generated code directly. The theory is that we would probably never have to modify this code, since it's so intimately linked to the hardware; it's a bit like committing an include file with register offsets for a particular peripheral. |
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| .. | ||
| long_8khz.wav | ||
| midwinter_original.wav | ||
| README.md | ||
| rom.db | ||
| short_8khz.wav | ||
| short_cd.wav | ||
| soc.svd | ||
| soc_csr.bin | ||
Audio Samples
The .wav files included here are meant for audio testing only and are intended to be bundled into the final distribution. Developers who want to use this for testing will need to manually stage and load these samples into the correct location in the FLASH. See https://github.com/betrusted-io/xous-core/blob/master/docs/flash.md for the locations of the samples.
tools/usb_update.py can provision the "long_8khz.wav" sample that is used
by the latest demo of audio playback in xous-core.
The track samples included here are from "Midwinter", by Jackalope (https://soundcloud.com/tokyojackalope)
Used with permission to redistribute as part of this repository.
SoC Prebuild
A copy of a pre-built FPGA SoC binary that matches the latest version of the current tree is also included here. It's recommended to flash this pre-build FPGA image so your kernel matches the hardware if you're only building the kernel from scratch, and not also building the FPGA hardware.