mirror of
https://github.com/saymrwulf/xous-core.git
synced 2026-11-08 04:56:43 +00:00
34 lines
635 B
Text
34 lines
635 B
Text
cpu: CPU.VexRiscv @ sysbus
|
|
cpuType: "rv32i"
|
|
PerformanceInMips: 6
|
|
|
|
uart: UART.LiteX_UART @ {
|
|
sysbus 0xE0001800
|
|
}
|
|
-> cpu@1000
|
|
|
|
timer0: Timers.LiteX_Timer_32 @ {
|
|
sysbus 0xe0002000
|
|
}
|
|
frequency: 100000000
|
|
-> cpu@1001
|
|
|
|
sram: Memory.MappedMemory @ {
|
|
sysbus 0x10000000;
|
|
sysbus 0x90000000 // shadow
|
|
}
|
|
size: 0x00020000
|
|
|
|
ticktimer: Timers.TickTimer @ sysbus 0xe0005000
|
|
periodInMs: 1
|
|
-> cpu @ 1003
|
|
|
|
flash_mem: Memory.MappedMemory @ {
|
|
sysbus 0x20000000;
|
|
sysbus 0xA0000000 // shadow
|
|
}
|
|
size: 0x8000000
|
|
|
|
sysbus:
|
|
init:
|
|
ApplySVD @ec/soc.svd
|