mirror of https://github.com/saymrwulf/xous-core.git synced 2026-11-04 04:27:34 +00:00

History

Sean Cross f2e9d2b76c kernel: riscv: threads: ensure registers are zeroed The register set should be cleared already, however it is possible (though remote) that register values are not cleared when a thread is created. Ordinarily threads are zeroed when destroyed, but this makes sure they're zeroed upon creation as well. Signed-off-by: Sean Cross <sean@xobs.io>		2023-12-25 23:29:20 +08:00
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src	kernel: riscv: threads: ensure registers are zeroed	2023-12-25 23:29:20 +08:00
assemble.ps1
assemble.sh
build.rs
Cargo.toml	bump pins as xous-rs has changed	2023-12-01 21:20:01 +08:00
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README.md

README.md

Xous Kernel

This contains the core kernel for Xous. It requires a stage 1 loader in order to start up, as it assumes the system is already running in Supervisor mode.

Building

To build the kernel, you will need a riscv32 target for Rust. Possible targets include riscv32i-unknown-none-elf, riscv32imac-unknown-none-elf, or riscv32imac-unknown-xous-elf.

Decide what target you want. For simple, embedded systems this could be riscv32i-unknown-none-elf, and for more complex systems with compressed instructions you could use riscv32imac-unknown-none-elf.
Get Rust. Go to https://rustup.rs/ and follow its instructions.
Install the proper toolchain: rustup target add ${target_arch}
Build the kernel: cargo build --release --target ${target_arch}

Using

To use the kernel, you must package it up into an arguments binary with xous-tools.

Testing

TBD

Contribution Guidelines

Please see CONTRIBUTING for details on how to make a contribution.

Please note that this project is released with a Contributor Code of Conduct. By participating in this project you agree to abide its terms.

License

This project is licensed under the Apache License 2.0 LICENSE. For accurate information, please check individual files.