xous-core/svd2repl/src
Sean Cross b12c08e998 emulation: soc: add _zicsr_zifencei to rv32imac
Add "_zicsr_zifencei" to "rv32imac" when describing the CPU core. This
is required by newer versions of the spec, and will eventually be a
requirement of Renode.

Signed-off-by: Sean Cross <sean@xobs.io>
2023-12-29 18:42:16 +08:00
..
generate.rs emulation: soc: add _zicsr_zifencei to rv32imac 2023-12-29 18:42:16 +08:00
lib.rs svd2repl: add program to generate a repl file 2021-05-19 14:12:01 +08:00
main.rs remove clap from svd2repl 2022-09-29 22:31:50 +08:00