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xous-core/emulation/soc/renode.svd

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<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>litex</vendor>
<name>SOC</name>
<description><![CDATA[Litex SoC 2021-08-29 18:32:03]]></description>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>REBOOT</name>
<baseAddress>0xF0000000</baseAddress>
<groupName>REBOOT</groupName>
<registers>
<register>
<name>SOC_RESET</name>
<description><![CDATA[Writing 0xAC to this register will do a full SoC reset, including CRGs and
peripherals]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>soc_reset</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>ADDR</name>
<description><![CDATA[The address written here will be used as the next reset vector]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x80000000</resetValue>
<size>32</size>
<fields>
<field>
<name>addr</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>CPU_RESET</name>
<description><![CDATA[Writing anything to this register resets the CPU, and the CPU only; does not
affect CRG or peripherals]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>cpu_reset</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0xc</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>TIMER0</name>
<baseAddress>0xF0001000</baseAddress>
<groupName>TIMER0</groupName>
<registers>
<register>
<name>LOAD</name>
<description><![CDATA[Load value when Timer is (re-)enabled. In One-Shot mode, the value written to
this register specifies the Timer's duration in clock cycles.]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>load</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RELOAD</name>
<description><![CDATA[Reload value when Timer reaches ``0``. In Periodic mode, the value written to
this register specify the Timer's period in clock cycles.]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>reload</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>EN</name>
<description><![CDATA[Enable flag of the Timer. Set this flag to ``1`` to enable/start the Timer. Set
to ``0`` to disable the Timer.]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>en</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[This register contains the current raw level of the zero event trigger. Writes
to this register have no effect.]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>zero</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``zero`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[When a zero event occurs, the corresponding bit will be set in this register.
To clear the Event, set the corresponding bit in this register.]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>zero</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[`1` if a `zero` event occurred. This Event is triggered on a **falling** edge.]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[This register enables the corresponding zero events. Write a ``0`` to this
register to disable individual events.]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>zero</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``zero`` Event]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>timer0</name>
<value>0</value>
</interrupt>
</peripheral>
<peripheral>
<name>CRG</name>
<baseAddress>0xF0002000</baseAddress>
<groupName>CRG</groupName>
<registers>
<register>
<name>MMCM_DRP_RESET</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>mmcm_drp_reset</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>MMCM_DRP_LOCKED</name>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>mmcm_drp_locked</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>MMCM_DRP_READ</name>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>mmcm_drp_read</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>MMCM_DRP_WRITE</name>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>mmcm_drp_write</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>MMCM_DRP_DRDY</name>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>mmcm_drp_drdy</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>MMCM_DRP_ADR</name>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>mmcm_drp_adr</name>
<msb>6</msb>
<bitRange>[6:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>MMCM_DRP_DAT_W</name>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>mmcm_drp_dat_w</name>
<msb>15</msb>
<bitRange>[15:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>MMCM_DRP_DAT_R</name>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>mmcm_drp_dat_r</name>
<msb>15</msb>
<bitRange>[15:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>GPIO</name>
<baseAddress>0xF0003000</baseAddress>
<groupName>GPIO</groupName>
<registers>
<register>
<name>OUTPUT</name>
<description><![CDATA[Values to appear on GPIO when respective `drive` bit is asserted]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>output</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>INPUT</name>
<description><![CDATA[Value measured on the respective GPIO pin]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>input</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DRIVE</name>
<description><![CDATA[When a bit is set to `1`, the respective pad drives its value out]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>drive</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>INTENA</name>
<description><![CDATA[Enable interrupts when a respective bit is set]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>intena</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>INTPOL</name>
<description><![CDATA[When a bit is `1`, falling-edges cause interrupts. Otherwise, rising edges cause
interrupts.]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>intpol</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>UARTSEL</name>
<description><![CDATA[Used to select which UART is routed to physical pins, 00 = kernel debug, 01 =
console, others reserved based on build]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>uartsel</name>
<msb>1</msb>
<bitRange>[1:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DEBUG</name>
<description><![CDATA[Various debugging configurations]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>wfi</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Whet set, patches CRG powerdown into GPIO0 instead of the usual data line. Must
configure as output for the value to appear on the pin]]></description>
</field>
<field>
<name>wakeup</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Whet set, patches wakeup signal into GPIO1 instead of the usual data line. Must
configure as output for the value to appear on the pin]]></description>
</field>
</fields>
</register>
<register>
<name>USBDISABLE</name>
<description><![CDATA[When set to ``1``, USB debug is limited by remapping all wishbone request
addresses to 0x8000_0000]]></description>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>usbdisable</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[This register contains the current raw level of the event7 event trigger.
Writes to this register have no effect.]]></description>
<addressOffset>0x0020</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>event0</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``event0`` event]]></description>
</field>
<field>
<name>event1</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Level of the ``event1`` event]]></description>
</field>
<field>
<name>event2</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Level of the ``event2`` event]]></description>
</field>
<field>
<name>event3</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[Level of the ``event3`` event]]></description>
</field>
<field>
<name>event4</name>
<msb>4</msb>
<bitRange>[4:4]</bitRange>
<lsb>4</lsb>
<description><![CDATA[Level of the ``event4`` event]]></description>
</field>
<field>
<name>event5</name>
<msb>5</msb>
<bitRange>[5:5]</bitRange>
<lsb>5</lsb>
<description><![CDATA[Level of the ``event5`` event]]></description>
</field>
<field>
<name>event6</name>
<msb>6</msb>
<bitRange>[6:6]</bitRange>
<lsb>6</lsb>
<description><![CDATA[Level of the ``event6`` event]]></description>
</field>
<field>
<name>event7</name>
<msb>7</msb>
<bitRange>[7:7]</bitRange>
<lsb>7</lsb>
<description><![CDATA[Level of the ``event7`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[When a event7 event occurs, the corresponding bit will be set in this register.
To clear the Event, set the corresponding bit in this register.]]></description>
<addressOffset>0x0024</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>event0</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[`1` if a this particular event occurred. This Event is triggered on a **rising**
edge.]]></description>
</field>
<field>
<name>event1</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[`1` if a this particular event occurred. This Event is triggered on a **rising**
edge.]]></description>
</field>
<field>
<name>event2</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[`1` if a this particular event occurred. This Event is triggered on a **rising**
edge.]]></description>
</field>
<field>
<name>event3</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[`1` if a this particular event occurred. This Event is triggered on a **rising**
edge.]]></description>
</field>
<field>
<name>event4</name>
<msb>4</msb>
<bitRange>[4:4]</bitRange>
<lsb>4</lsb>
<description><![CDATA[`1` if a this particular event occurred. This Event is triggered on a **rising**
edge.]]></description>
</field>
<field>
<name>event5</name>
<msb>5</msb>
<bitRange>[5:5]</bitRange>
<lsb>5</lsb>
<description><![CDATA[`1` if a this particular event occurred. This Event is triggered on a **rising**
edge.]]></description>
</field>
<field>
<name>event6</name>
<msb>6</msb>
<bitRange>[6:6]</bitRange>
<lsb>6</lsb>
<description><![CDATA[`1` if a this particular event occurred. This Event is triggered on a **rising**
edge.]]></description>
</field>
<field>
<name>event7</name>
<msb>7</msb>
<bitRange>[7:7]</bitRange>
<lsb>7</lsb>
<description><![CDATA[`1` if a this particular event occurred. This Event is triggered on a **rising**
edge.]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[This register enables the corresponding event7 events. Write a ``0`` to this
register to disable individual events.]]></description>
<addressOffset>0x0028</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>event0</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``event0`` Event]]></description>
</field>
<field>
<name>event1</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Write a ``1`` to enable the ``event1`` Event]]></description>
</field>
<field>
<name>event2</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Write a ``1`` to enable the ``event2`` Event]]></description>
</field>
<field>
<name>event3</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[Write a ``1`` to enable the ``event3`` Event]]></description>
</field>
<field>
<name>event4</name>
<msb>4</msb>
<bitRange>[4:4]</bitRange>
<lsb>4</lsb>
<description><![CDATA[Write a ``1`` to enable the ``event4`` Event]]></description>
</field>
<field>
<name>event5</name>
<msb>5</msb>
<bitRange>[5:5]</bitRange>
<lsb>5</lsb>
<description><![CDATA[Write a ``1`` to enable the ``event5`` Event]]></description>
</field>
<field>
<name>event6</name>
<msb>6</msb>
<bitRange>[6:6]</bitRange>
<lsb>6</lsb>
<description><![CDATA[Write a ``1`` to enable the ``event6`` Event]]></description>
</field>
<field>
<name>event7</name>
<msb>7</msb>
<bitRange>[7:7]</bitRange>
<lsb>7</lsb>
<description><![CDATA[Write a ``1`` to enable the ``event7`` Event]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x2c</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>gpio</name>
<value>1</value>
</interrupt>
</peripheral>
<peripheral>
<name>UART</name>
<baseAddress>0xF0005000</baseAddress>
<groupName>UART</groupName>
<registers>
<register>
<name>RXTX</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rxtx</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>TXFULL</name>
<description><![CDATA[TX FIFO Full.]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>txfull</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RXEMPTY</name>
<description><![CDATA[RX FIFO Empty.]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rxempty</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[This register contains the current raw level of the rx event trigger. Writes to
this register have no effect.]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>tx</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``tx`` event]]></description>
</field>
<field>
<name>rx</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Level of the ``rx`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[When a rx event occurs, the corresponding bit will be set in this register. To
clear the Event, set the corresponding bit in this register.]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>tx</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[`1` if a `tx` event occurred. This Event is triggered on a **falling** edge.]]></description>
</field>
<field>
<name>rx</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[`1` if a `rx` event occurred. This Event is triggered on a **falling** edge.]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[This register enables the corresponding rx events. Write a ``0`` to this
register to disable individual events.]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>tx</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``tx`` Event]]></description>
</field>
<field>
<name>rx</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Write a ``1`` to enable the ``rx`` Event]]></description>
</field>
</fields>
</register>
<register>
<name>TXEMPTY</name>
<description><![CDATA[TX FIFO Empty.]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>txempty</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RXFULL</name>
<description><![CDATA[RX FIFO Full.]]></description>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rxfull</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>uart</name>
<value>2</value>
</interrupt>
</peripheral>
<peripheral>
<name>CONSOLE</name>
<baseAddress>0xF0007000</baseAddress>
<groupName>CONSOLE</groupName>
<registers>
<register>
<name>RXTX</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rxtx</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>TXFULL</name>
<description><![CDATA[TX FIFO Full.]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>txfull</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RXEMPTY</name>
<description><![CDATA[RX FIFO Empty.]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rxempty</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[This register contains the current raw level of the rx event trigger. Writes to
this register have no effect.]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>tx</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``tx`` event]]></description>
</field>
<field>
<name>rx</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Level of the ``rx`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[When a rx event occurs, the corresponding bit will be set in this register. To
clear the Event, set the corresponding bit in this register.]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>tx</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[`1` if a `tx` event occurred. This Event is triggered on a **falling** edge.]]></description>
</field>
<field>
<name>rx</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[`1` if a `rx` event occurred. This Event is triggered on a **falling** edge.]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[This register enables the corresponding rx events. Write a ``0`` to this
register to disable individual events.]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>tx</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``tx`` Event]]></description>
</field>
<field>
<name>rx</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Write a ``1`` to enable the ``rx`` Event]]></description>
</field>
</fields>
</register>
<register>
<name>TXEMPTY</name>
<description><![CDATA[TX FIFO Empty.]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>txempty</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RXFULL</name>
<description><![CDATA[RX FIFO Full.]]></description>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rxfull</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>console</name>
<value>3</value>
</interrupt>
</peripheral>
<peripheral>
<name>APP_UART</name>
<baseAddress>0xF0009000</baseAddress>
<groupName>APP_UART</groupName>
<registers>
<register>
<name>RXTX</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rxtx</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>TXFULL</name>
<description><![CDATA[TX FIFO Full.]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>txfull</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RXEMPTY</name>
<description><![CDATA[RX FIFO Empty.]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rxempty</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[This register contains the current raw level of the rx event trigger. Writes to
this register have no effect.]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>tx</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``tx`` event]]></description>
</field>
<field>
<name>rx</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Level of the ``rx`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[When a rx event occurs, the corresponding bit will be set in this register. To
clear the Event, set the corresponding bit in this register.]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>tx</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[`1` if a `tx` event occurred. This Event is triggered on a **falling** edge.]]></description>
</field>
<field>
<name>rx</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[`1` if a `rx` event occurred. This Event is triggered on a **falling** edge.]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[This register enables the corresponding rx events. Write a ``0`` to this
register to disable individual events.]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>tx</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``tx`` Event]]></description>
</field>
<field>
<name>rx</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Write a ``1`` to enable the ``rx`` Event]]></description>
</field>
</fields>
</register>
<register>
<name>TXEMPTY</name>
<description><![CDATA[TX FIFO Empty.]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>txempty</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RXFULL</name>
<description><![CDATA[RX FIFO Full.]]></description>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rxfull</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>app_uart</name>
<value>4</value>
</interrupt>
</peripheral>
<peripheral>
<name>INFO</name>
<baseAddress>0xF000A000</baseAddress>
<groupName>INFO</groupName>
<registers>
<register>
<name>DNA_ID1</name>
<description><![CDATA[Bits 32-56 of `INFO_DNA_ID`.]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>dna_id</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DNA_ID0</name>
<description><![CDATA[Bits 0-31 of `INFO_DNA_ID`.]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>dna_id</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>GIT_MAJOR</name>
<description><![CDATA[Major git tag version. For example, this firmware was built from git tag
``v0.9.0``, so this value is ``0``.]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>git_major</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>GIT_MINOR</name>
<description><![CDATA[Minor git tag version. For example, this firmware was built from git tag
``v0.9.0``, so this value is ``9``.]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x09</resetValue>
<size>32</size>
<fields>
<field>
<name>git_minor</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>GIT_REVISION</name>
<description><![CDATA[Revision git tag version. For example, this firmware was built from git tag
``v0.9.0``, so this value is ``0``.]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>git_revision</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>GIT_GITREV</name>
<description><![CDATA[First 32-bits of the git revision. This documentation was built from git rev
``b481fff0``, so this value is 3028418544, which should be enough to check out
the exact git version used to build this firmware.]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0xb481fff0</resetValue>
<size>32</size>
<fields>
<field>
<name>git_gitrev</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>GIT_GITEXTRA</name>
<description><![CDATA[The number of additional commits beyond the git tag. For example, if this value
is ``1``, then the repository this was built from has one additional commit
beyond the tag indicated in `MAJOR`, `MINOR`, and `REVISION`.]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x0e</resetValue>
<size>32</size>
<fields>
<field>
<name>git_gitextra</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>GIT_DIRTY</name>
<addressOffset>0x001c</addressOffset>
<resetValue>0x01</resetValue>
<size>32</size>
<fields>
<field>
<name>dirty</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Set to ``1`` if this device was built from a git repo with uncommitted
modifications.]]></description>
</field>
</fields>
</register>
<register>
<name>PLATFORM_PLATFORM1</name>
<description><![CDATA[Bits 32-63 of `INFO_PLATFORM_PLATFORM`.]]></description>
<addressOffset>0x0020</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>platform_platform</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>PLATFORM_PLATFORM0</name>
<description><![CDATA[Bits 0-31 of `INFO_PLATFORM_PLATFORM`.]]></description>
<addressOffset>0x0024</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>platform_platform</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>PLATFORM_TARGET1</name>
<description><![CDATA[Bits 32-63 of `INFO_PLATFORM_TARGET`.]]></description>
<addressOffset>0x0028</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>platform_target</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>PLATFORM_TARGET0</name>
<description><![CDATA[Bits 0-31 of `INFO_PLATFORM_TARGET`.]]></description>
<addressOffset>0x002c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>platform_target</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x30</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>SRAM_EXT</name>
<baseAddress>0xF000B000</baseAddress>
<groupName>SRAM_EXT</groupName>
<registers>
<register>
<name>CONFIG_STATUS</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>mode</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[The current configuration mode of the SRAM]]></description>
</field>
</fields>
</register>
<register>
<name>READ_CONFIG</name>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>trigger</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Writing to this bit triggers the SRAM mode status read update]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>MEMLCD</name>
<baseAddress>0xF000C000</baseAddress>
<groupName>MEMLCD</groupName>
<registers>
<register>
<name>COMMAND</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>UpdateDirty</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to flush dirty lines to the LCD]]></description>
</field>
<field>
<name>UpdateAll</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Update full screen regardless of tag state]]></description>
</field>
</fields>
</register>
<register>
<name>BUSY</name>
<description><![CDATA[A ``1`` indicates that the block is currently updating the LCD]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>busy</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>PRESCALER</name>
<description><![CDATA[Prescaler value. LCD clock is module ``(clock / (prescaler+1))``. Reset value:
``99``, so for a default sysclk of 100MHz this yields an LCD ``SCLK`` of 1MHz]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x63</resetValue>
<size>32</size>
<fields>
<field>
<name>prescaler</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[This register contains the current raw level of the done event trigger. Writes
to this register have no effect.]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>done</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``done`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[When a done event occurs, the corresponding bit will be set in this register.
To clear the Event, set the corresponding bit in this register.]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>done</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[`1` if a `done` event occurred. This Event is triggered on a **falling** edge.]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[This register enables the corresponding done events. Write a ``0`` to this
register to disable individual events.]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>done</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``done`` Event]]></description>
</field>
</fields>
</register>
<register>
<name>DEVBOOT</name>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>devboot</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[When set to ``1``, permanently add a strike-through on the top of the screen.
Cannot be cleared, except by a full reset. Do not rely on this register to
determine if a devboot has happened; the *register* may be cleared, but the
internal hardware bit cannot be.]]></description>
</field>
</fields>
</register>
<register>
<name>DEVSTATUS</name>
<description><![CDATA[Reads back as ``1`` if a devboot was set anywhere along the boot chain. This is
a read-only register and reflects ground truth.]]></description>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>devstatus</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>COM</name>
<baseAddress>0xF000D000</baseAddress>
<groupName>COM</groupName>
<registers>
<register>
<name>TX</name>
<description><![CDATA[Tx data, for COPI. Note: 32-bit CSRs are required for this block to work!]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>tx</name>
<msb>15</msb>
<bitRange>[15:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RX</name>
<description><![CDATA[Rx data, from CIPO]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rx</name>
<msb>15</msb>
<bitRange>[15:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>CONTROL</name>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>intena</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Enable interrupt on transaction finished]]></description>
</field>
<field>
<name>autohold</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Disallow transmission start if hold if asserted]]></description>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>tip</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Set when transaction is in progress]]></description>
</field>
<field>
<name>hold</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Set when peripheral asserts hold]]></description>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[This register contains the current raw level of the spi_hold event trigger.
Writes to this register have no effect.]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>spi_int</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``spi_int`` event]]></description>
</field>
<field>
<name>spi_hold</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Level of the ``spi_hold`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[When a spi_hold event occurs, the corresponding bit will be set in this
register. To clear the Event, set the corresponding bit in this register.]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>spi_int</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[`1` if a `spi_int` event occurred. This Event is triggered on a **falling**
edge.]]></description>
</field>
<field>
<name>spi_hold</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[`1` if a `spi_hold` event occurred. This Event is triggered on a **falling**
edge.]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[This register enables the corresponding spi_hold events. Write a ``0`` to this
register to disable individual events.]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>spi_int</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``spi_int`` Event]]></description>
</field>
<field>
<name>spi_hold</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Write a ``1`` to enable the ``spi_hold`` Event]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x1c</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>com</name>
<value>5</value>
</interrupt>
</peripheral>
<peripheral>
<name>I2C</name>
<baseAddress>0xF000E000</baseAddress>
<groupName>I2C</groupName>
<registers>
<register>
<name>PRESCALE</name>
<description><![CDATA[Prescaler value. Set to (module clock / (5 * I2C freq) - 1). Example: if module
clock is equal to sysclk; syclk is 100MHz; and I2C freq is 100kHz, then
prescaler is (100MHz / (5 * 100kHz) - 1) = 199. Reset value: 0xFFFF]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0xffff</resetValue>
<size>32</size>
<fields>
<field>
<name>prescale</name>
<msb>15</msb>
<bitRange>[15:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>CONTROL</name>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>Resvd</name>
<msb>5</msb>
<bitRange>[5:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Reserved (for cross-compatibility with OpenCores drivers)]]></description>
</field>
<field>
<name>IEN</name>
<msb>6</msb>
<bitRange>[6:6]</bitRange>
<lsb>6</lsb>
<description><![CDATA[When set to `1`, interrupts are enabled.]]></description>
</field>
<field>
<name>EN</name>
<msb>7</msb>
<bitRange>[7:7]</bitRange>
<lsb>7</lsb>
<description><![CDATA[When set to `1`, the core is enabled.]]></description>
</field>
</fields>
</register>
<register>
<name>TXR</name>
<description><![CDATA[Next byte to transmit to slave devices. LSB indicates R/W during address phases,
`1` for reading from slaves, `0` for writing to slaves]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>txr</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RXR</name>
<description><![CDATA[Data being read from slaved devices]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rxr</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>COMMAND</name>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>IACK</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Interrupt acknowledge; when set, clears a pending interrupt]]></description>
</field>
<field>
<name>Resvd</name>
<msb>2</msb>
<bitRange>[2:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[reserved for cross-compatibility with OpenCores drivers]]></description>
</field>
<field>
<name>ACK</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[when a receiver, sent ack (`ACK=0`) or nack (`ACK=1`)]]></description>
</field>
<field>
<name>WR</name>
<msb>4</msb>
<bitRange>[4:4]</bitRange>
<lsb>4</lsb>
<description><![CDATA[write to slave]]></description>
</field>
<field>
<name>RD</name>
<msb>5</msb>
<bitRange>[5:5]</bitRange>
<lsb>5</lsb>
<description><![CDATA[read from slave]]></description>
</field>
<field>
<name>STO</name>
<msb>6</msb>
<bitRange>[6:6]</bitRange>
<lsb>6</lsb>
<description><![CDATA[generate stop condition]]></description>
</field>
<field>
<name>STA</name>
<msb>7</msb>
<bitRange>[7:7]</bitRange>
<lsb>7</lsb>
<description><![CDATA[generate (repeated) start condition]]></description>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>IF</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Interrupt flag, This bit is set when an interrupt is pending, which will cause a
processor interrupt request if the IEN bit is set. The Interrupt Flag is set
upon the completion of one byte of data transfer.]]></description>
</field>
<field>
<name>TIP</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[transfer in progress]]></description>
</field>
<field>
<name>Resvd</name>
<msb>4</msb>
<bitRange>[4:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[reserved for cross-compatibility with OpenCores drivers]]></description>
</field>
<field>
<name>ArbLost</name>
<msb>5</msb>
<bitRange>[5:5]</bitRange>
<lsb>5</lsb>
<description><![CDATA[Set when arbitration for the bus is lost]]></description>
</field>
<field>
<name>Busy</name>
<msb>6</msb>
<bitRange>[6:6]</bitRange>
<lsb>6</lsb>
<description><![CDATA[I2C block is busy processing the latest command]]></description>
</field>
<field>
<name>RxACK</name>
<msb>7</msb>
<bitRange>[7:7]</bitRange>
<lsb>7</lsb>
<description><![CDATA[Received acknowledge from slave. 1 = no ack received, 0 = ack received]]></description>
</field>
</fields>
</register>
<register>
<name>CORE_RESET</name>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>reset</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write `1` for a synchronous reset of the I2C core. Does not reset the prescale
value. This signal is outside of the OpenCores spec.]]></description>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[Triggered on the falling edge of TIP]]></description>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>i2c_int</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``i2c_int`` event]]></description>
</field>
<field>
<name>txrx_done</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Level of the ``txrx_done`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[Triggered on the falling edge of TIP]]></description>
<addressOffset>0x0020</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>i2c_int</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Triggered when arbitration is lost or transaction done. Requires IACK write to
clear or else it will re-trigger.]]></description>
</field>
<field>
<name>txrx_done</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Triggered on the falling edge of TIP]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[Triggered on the falling edge of TIP]]></description>
<addressOffset>0x0024</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>i2c_int</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``i2c_int`` Event]]></description>
</field>
<field>
<name>txrx_done</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Write a ``1`` to enable the ``txrx_done`` Event]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x28</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>i2c</name>
<value>6</value>
</interrupt>
</peripheral>
<peripheral>
<name>BTEVENTS</name>
<baseAddress>0xF000F000</baseAddress>
<groupName>BTEVENTS</groupName>
<registers>
<register>
<name>EV_STATUS</name>
<description><![CDATA[This register contains the current raw level of the rtc_int event trigger.
Writes to this register have no effect.]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>com_int</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``com_int`` event]]></description>
</field>
<field>
<name>rtc_int</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Level of the ``rtc_int`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[When a rtc_int event occurs, the corresponding bit will be set in this
register. To clear the Event, set the corresponding bit in this register.]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>com_int</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[`1` if a `com_int` event occurred. This Event is triggered on a **rising** edge.]]></description>
</field>
<field>
<name>rtc_int</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[`1` if a `rtc_int` event occurred. This Event is triggered on a **falling**
edge.]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[This register enables the corresponding rtc_int events. Write a ``0`` to this
register to disable individual events.]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>com_int</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``com_int`` Event]]></description>
</field>
<field>
<name>rtc_int</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Write a ``1`` to enable the ``rtc_int`` Event]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0xc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>btevents</name>
<value>7</value>
</interrupt>
</peripheral>
<peripheral>
<name>MESSIBLE</name>
<baseAddress>0xF0010000</baseAddress>
<groupName>MESSIBLE</groupName>
<registers>
<register>
<name>IN</name>
<description><![CDATA[Write half of the FIFO to send data out the Messible. Writing to this register
advances the write pointer automatically.]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>in</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>OUT</name>
<description><![CDATA[Read half of the FIFO to receive data on the Messible. Reading from this
register advances the read pointer automatically.]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>out</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>full</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[`0` if more data can fit into the IN FIFO.]]></description>
</field>
<field>
<name>have</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[`1` if data can be read from the OUT FIFO.]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0xc</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>MESSIBLE2</name>
<baseAddress>0xF0011000</baseAddress>
<groupName>MESSIBLE2</groupName>
<registers>
<register>
<name>IN</name>
<description><![CDATA[Write half of the FIFO to send data out the Messible. Writing to this register
advances the write pointer automatically.]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>in</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>OUT</name>
<description><![CDATA[Read half of the FIFO to receive data on the Messible. Reading from this
register advances the read pointer automatically.]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>out</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>full</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[`0` if more data can fit into the IN FIFO.]]></description>
</field>
<field>
<name>have</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[`1` if data can be read from the OUT FIFO.]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0xc</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>TICKTIMER</name>
<baseAddress>0xF0012000</baseAddress>
<groupName>TICKTIMER</groupName>
<registers>
<register>
<name>CONTROL</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>reset</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a `1` to this bit to reset the count to 0. This bit has priority over all
other requests.]]></description>
</field>
</fields>
</register>
<register>
<name>TIME1</name>
<description><![CDATA[Bits 32-63 of `TICKTIMER_TIME`. Elapsed time in systicks]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>time</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>TIME0</name>
<description><![CDATA[Bits 0-31 of `TICKTIMER_TIME`.]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>time</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>MSLEEP_TARGET1</name>
<description><![CDATA[Bits 32-63 of `TICKTIMER_MSLEEP_TARGET`. Target time in 1.0ms ticks]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>msleep_target</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>MSLEEP_TARGET0</name>
<description><![CDATA[Bits 0-31 of `TICKTIMER_MSLEEP_TARGET`.]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>msleep_target</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[This register contains the current raw level of the alarm event trigger. Writes
to this register have no effect.]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>alarm</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``alarm`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[When a alarm event occurs, the corresponding bit will be set in this register.
To clear the Event, set the corresponding bit in this register.]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>alarm</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[`1` if a `alarm` event occurred. This Event is **level triggered** when the
signal is **high**.]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[This register enables the corresponding alarm events. Write a ``0`` to this
register to disable individual events.]]></description>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>alarm</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``alarm`` Event]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ticktimer</name>
<value>8</value>
</interrupt>
</peripheral>
<peripheral>
<name>SUSRES</name>
<baseAddress>0xF0013000</baseAddress>
<groupName>SUSRES</groupName>
<registers>
<register>
<name>CONTROL</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>pause</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a `1` to this field to request a pause to counting, 0 for free-run. Count
pauses on the next tick quanta.]]></description>
</field>
<field>
<name>load</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[If paused, write a `1` to this bit to load a resume value to the timer. If not
paused, this bit is ignored.]]></description>
</field>
</fields>
</register>
<register>
<name>RESUME_TIME1</name>
<description><![CDATA[Bits 32-63 of `SUSRES_RESUME_TIME`. Elapsed time to load. Loaded upon writing
`1` to the load bit in the control register. This will immediately affect the
msleep extension.]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>resume_time</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RESUME_TIME0</name>
<description><![CDATA[Bits 0-31 of `SUSRES_RESUME_TIME`.]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>resume_time</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>TIME1</name>
<description><![CDATA[Bits 32-63 of `SUSRES_TIME`. Cycle-accurate mirror copy of time in systicks,
from the TickTimer]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>time</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>TIME0</name>
<description><![CDATA[Bits 0-31 of `SUSRES_TIME`.]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>time</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>paused</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[When set, indicates that the counter has been paused]]></description>
</field>
</fields>
</register>
<register>
<name>STATE</name>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>resume</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Used to transfer the resume state information from the loader to Xous. If set,
indicates we are on the resume half of a suspend/resume.]]></description>
</field>
<field>
<name>was_forced</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Used by the bootloader to indicate to the kernel if the current resume was from
a forced suspend (e.g. a timeout happened and a server may be unclean.]]></description>
</field>
</fields>
</register>
<register>
<name>POWERDOWN</name>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>powerdown</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a `1` to force an immediate powerdown. Use with care.]]></description>
</field>
</fields>
</register>
<register>
<name>WFI</name>
<addressOffset>0x0020</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>override</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a `1` to this register to disable WFI (used to make sure the
suspend/resume is not interrupted by a CPU sleep cal)]]></description>
</field>
</fields>
</register>
<register>
<name>INTERRUPT</name>
<addressOffset>0x0024</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>interrupt</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Writing this causes an interrupt to fire. Used by Xous to initiate
suspend/resume from an interrupt context.]]></description>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[This register contains the current raw level of the soft_int event trigger.
Writes to this register have no effect.]]></description>
<addressOffset>0x0028</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>soft_int</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``soft_int`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[When a soft_int event occurs, the corresponding bit will be set in this
register. To clear the Event, set the corresponding bit in this register.]]></description>
<addressOffset>0x002c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>soft_int</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[`1` if a `soft_int` event occurred. This Event is triggered on a **falling**
edge.]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[This register enables the corresponding soft_int events. Write a ``0`` to this
register to disable individual events.]]></description>
<addressOffset>0x0030</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>soft_int</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``soft_int`` Event]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x34</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>susres</name>
<value>9</value>
</interrupt>
</peripheral>
<peripheral>
<name>POWER</name>
<baseAddress>0xF0014000</baseAddress>
<groupName>POWER</groupName>
<registers>
<register>
<name>POWER</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x20a</resetValue>
<size>32</size>
<fields>
<field>
<name>audio</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write `1` to power on the audio subsystem]]></description>
</field>
<field>
<name>self</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Writing `1` forces self power-on (overrides the EC's ability to power me down)]]></description>
</field>
<field>
<name>ec_snoop</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Writing `1` allows the insecure EC to snoop a couple keyboard pads for wakeup
key sequence recognition]]></description>
</field>
<field>
<name>state</name>
<msb>4</msb>
<bitRange>[4:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[Current SoC power state. 0x=off or not ready, 10=on and safe to shutdown, 11=on
and not safe to shut down, resets to 01 to allow extSRAM access immediately
during init]]></description>
</field>
<field>
<name>reset_ec</name>
<msb>5</msb>
<bitRange>[5:5]</bitRange>
<lsb>5</lsb>
<description><![CDATA[Writing a `1` forces EC into reset. Requires write of `0` to release reset.]]></description>
</field>
<field>
<name>up5k_on</name>
<msb>6</msb>
<bitRange>[6:6]</bitRange>
<lsb>6</lsb>
<description><![CDATA[Writing a `1` pulses the UP5K domain to turn on]]></description>
</field>
<field>
<name>boostmode</name>
<msb>7</msb>
<bitRange>[7:7]</bitRange>
<lsb>7</lsb>
<description><![CDATA[Writing a `1` causes the USB port to source 5V. To be active only when playing
the host role.]]></description>
</field>
<field>
<name>selfdestruct</name>
<msb>8</msb>
<bitRange>[8:8]</bitRange>
<lsb>8</lsb>
<description><![CDATA[Set this bit to clear BBRAM AES key (if used) and cut power in an annoying-to-
reset fashion]]></description>
</field>
<field>
<name>crypto_on</name>
<msb>9</msb>
<bitRange>[9:9]</bitRange>
<lsb>9</lsb>
<description><![CDATA[Writing a `1` to this bit turns the clock on to the crypto accelerators.
Configured to currently override power to `on` at boot to ease system setup.]]></description>
</field>
<field>
<name>ignore_locked</name>
<msb>10</msb>
<bitRange>[10:10]</bitRange>
<lsb>10</lsb>
<description><![CDATA[Writing a `1` to this bit causes the reset to ignore the PLL lock status]]></description>
</field>
<field>
<name>disable_wfi</name>
<msb>11</msb>
<bitRange>[11:11]</bitRange>
<lsb>11</lsb>
<description><![CDATA[Writing a `1` to this bit causes WFI throttling to be disabled]]></description>
</field>
</fields>
</register>
<register>
<name>CLK_STATUS</name>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>crypto_on</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[The actual crypto clock power on signal, after OR'ing between three separate
sources (power, sha512, and engine25519)]]></description>
</field>
<field>
<name>sha_on</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Readback of SHA block power setting]]></description>
</field>
<field>
<name>engine_on</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Readback of Engine25519 block power setting]]></description>
</field>
<field>
<name>btpower_on</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[Readback of this block's override-on power setting]]></description>
</field>
</fields>
</register>
<register>
<name>WAKEUP_SOURCE</name>
<addressOffset>0x0008</addressOffset>
<resetValue>0xff</resetValue>
<size>32</size>
<fields>
<field>
<name>kbd</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Use the keyboard as wakeup source]]></description>
</field>
<field>
<name>ticktimer</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Use the ticktimer as wakeup source]]></description>
</field>
<field>
<name>timer0</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Use timer0 (os timer) as wakeup source]]></description>
</field>
<field>
<name>usb</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[Use USB k-transition as wakeup source]]></description>
</field>
<field>
<name>audio</name>
<msb>4</msb>
<bitRange>[4:4]</bitRange>
<lsb>4</lsb>
<description><![CDATA[Use audio FIFO empty as wakeup source]]></description>
</field>
<field>
<name>com</name>
<msb>5</msb>
<bitRange>[5:5]</bitRange>
<lsb>5</lsb>
<description><![CDATA[Use COM hold falling as wakeup source]]></description>
</field>
<field>
<name>rtc</name>
<msb>6</msb>
<bitRange>[6:6]</bitRange>
<lsb>6</lsb>
<description><![CDATA[Use RTC external interrupt as wakeup source]]></description>
</field>
<field>
<name>console</name>
<msb>7</msb>
<bitRange>[7:7]</bitRange>
<lsb>7</lsb>
<description><![CDATA[Use the console UART RX line dropping as wakeup source]]></description>
</field>
</fields>
</register>
<register>
<name>ACTIVITY_RATE</name>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>counts_awake</name>
<msb>30</msb>
<bitRange>[30:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[number of counts in the last sample interval that we were active]]></description>
</field>
</fields>
</register>
<register>
<name>SAMPLING_PERIOD</name>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>sample_period</name>
<msb>30</msb>
<bitRange>[30:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Sampling period for counts awake, in 12MHz cycles]]></description>
</field>
<field>
<name>kill_sampler</name>
<msb>31</msb>
<bitRange>[31:31]</bitRange>
<lsb>31</lsb>
<description><![CDATA[When set, permanently disable reporting (in case you don't want the high-
resolutionn timing sidechannel)]]></description>
</field>
</fields>
</register>
<register>
<name>VIBE</name>
<description><![CDATA[Vibration motor configuration register]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>vibe</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Turn on vibration motor]]></description>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[update available to activity register]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>usb_attach</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``usb_attach`` event]]></description>
</field>
<field>
<name>activity_update</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Level of the ``activity_update`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[update available to activity register]]></description>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>usb_attach</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[USB attach event]]></description>
</field>
<field>
<name>activity_update</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[update available to activity register]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[update available to activity register]]></description>
<addressOffset>0x0020</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>usb_attach</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``usb_attach`` Event]]></description>
</field>
<field>
<name>activity_update</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Write a ``1`` to enable the ``activity_update`` Event]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x24</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>power</name>
<value>10</value>
</interrupt>
</peripheral>
<peripheral>
<name>SPINOR_SOFT_INT</name>
<baseAddress>0xF0015000</baseAddress>
<groupName>SPINOR_SOFT_INT</groupName>
<registers>
<register>
<name>EV_STATUS</name>
<description><![CDATA[Used by software to trigger an interrupt context switch for SPINOR handlers.]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>spinor_int</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``spinor_int`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[Used by software to trigger an interrupt context switch for SPINOR handlers.]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>spinor_int</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Used by software to trigger an interrupt context switch for SPINOR handlers.]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[Used by software to trigger an interrupt context switch for SPINOR handlers.]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>spinor_int</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``spinor_int`` Event]]></description>
</field>
</fields>
</register>
<register>
<name>SOFTINT</name>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>softint</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Writing a `1` here triggers a software interrupt for the SPINOR server.]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>spinor_soft_int</name>
<value>11</value>
</interrupt>
</peripheral>
<peripheral>
<name>SPINOR</name>
<baseAddress>0xF0016000</baseAddress>
<groupName>SPINOR</groupName>
<registers>
<register>
<name>CONFIG</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x0a</resetValue>
<size>32</size>
<fields>
<field>
<name>dummy</name>
<msb>4</msb>
<bitRange>[4:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Number of dummy cycles]]></description>
</field>
</fields>
</register>
<register>
<name>DELAY_CONFIG</name>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>d</name>
<msb>4</msb>
<bitRange>[4:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Delay amount; each increment is 78ps]]></description>
</field>
<field>
<name>load</name>
<msb>5</msb>
<bitRange>[5:5]</bitRange>
<lsb>5</lsb>
<description><![CDATA[Force delay taps to delay_d]]></description>
</field>
</fields>
</register>
<register>
<name>DELAY_STATUS</name>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>q</name>
<msb>4</msb>
<bitRange>[4:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Readback of current delay amount, useful if inc/ce is used to set]]></description>
</field>
</fields>
</register>
<register>
<name>COMMAND</name>
<description><![CDATA[Write individual bits to issue special commands to SPI; setting multiple bits at
once leads to undefined behavior.]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>wakeup</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Sequence through init & wakeup routine]]></description>
</field>
<field>
<name>exec_cmd</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Writing a `1` executes a manual command]]></description>
</field>
<field>
<name>cmd_code</name>
<msb>9</msb>
<bitRange>[9:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Manual command code (first 8 bits, e.g. PP4B is 0x12)]]></description>
</field>
<field>
<name>has_arg</name>
<msb>10</msb>
<bitRange>[10:10]</bitRange>
<lsb>10</lsb>
<description><![CDATA[When set, transmits the value of `cmd_arg` as the argument to the command]]></description>
</field>
<field>
<name>dummy_cycles</name>
<msb>15</msb>
<bitRange>[15:11]</bitRange>
<lsb>11</lsb>
<description><![CDATA[Number of dummy cycles for manual command; 0 implies a write, >0 implies read]]></description>
</field>
<field>
<name>data_words</name>
<msb>23</msb>
<bitRange>[23:16]</bitRange>
<lsb>16</lsb>
<description><![CDATA[Number of data words (2x bytes)]]></description>
</field>
<field>
<name>lock_reads</name>
<msb>24</msb>
<bitRange>[24:24]</bitRange>
<lsb>24</lsb>
<description><![CDATA[When set, locks out read operations (recommended when doing programming)]]></description>
</field>
</fields>
</register>
<register>
<name>CMD_ARG</name>
<description><![CDATA[Command argument]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>cmd_arg</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Argument to manual command]]></description>
</field>
</fields>
</register>
<register>
<name>CMD_RBK_DATA</name>
<description><![CDATA[Readback data from commands]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>cmd_rbk_data</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Data read back from a cmd_code that has `write_code` set to 0]]></description>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description><![CDATA[Interface status]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>wip</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Operation in progress (write or erease)]]></description>
</field>
</fields>
</register>
<register>
<name>WDATA</name>
<description><![CDATA[Page data to write to FLASH]]></description>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>wdata</name>
<msb>15</msb>
<bitRange>[15:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[16-bit wide write data presented to FLASH, committed to a 128-entry deep FIFO.
Writes to this register are not cached; note that writes to the SPINOR address
space are also committed to the FIFO, but this space is cached by the CPU, and
therefore not guaranteed to be coherent or in order. The direct wishbone-write
address space is provisioned for e.g. USB bus masters that don't have caching.]]></description>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[An ECC event has happened on the current block; triggered by falling edge of
ECC_N]]></description>
<addressOffset>0x0020</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ecc_error</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``ecc_error`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[An ECC event has happened on the current block; triggered by falling edge of
ECC_N]]></description>
<addressOffset>0x0024</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ecc_error</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[An ECC event has happened on the current block; triggered by falling edge of
ECC_N]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[An ECC event has happened on the current block; triggered by falling edge of
ECC_N]]></description>
<addressOffset>0x0028</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ecc_error</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``ecc_error`` Event]]></description>
</field>
</fields>
</register>
<register>
<name>ECC_ADDRESS</name>
<addressOffset>0x002c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ecc_address</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Address of the most recent ECC event]]></description>
</field>
</fields>
</register>
<register>
<name>ECC_STATUS</name>
<addressOffset>0x0030</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ecc_error</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Live status of the ECS_N bit (ECC error on current packet when low)]]></description>
</field>
<field>
<name>ecc_overflow</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[More than one ECS_N event has happened since th last time ecc_address was
checked]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x34</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>spinor</name>
<value>12</value>
</interrupt>
</peripheral>
<peripheral>
<name>KEYBOARD</name>
<baseAddress>0xF0017000</baseAddress>
<groupName>KEYBOARD</groupName>
<registers>
<register>
<name>UART_CHAR</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>char</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[character value being injected]]></description>
</field>
<field>
<name>stb</name>
<msb>8</msb>
<bitRange>[8:8]</bitRange>
<lsb>8</lsb>
<description><![CDATA[current strobe value (for debugging)]]></description>
</field>
</fields>
</register>
<register>
<name>ROW0DAT</name>
<description><![CDATA[Column data for the given row]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>row0dat</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>ROW1DAT</name>
<description><![CDATA[Column data for the given row]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>row1dat</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>ROW2DAT</name>
<description><![CDATA[Column data for the given row]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>row2dat</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>ROW3DAT</name>
<description><![CDATA[Column data for the given row]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>row3dat</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>ROW4DAT</name>
<description><![CDATA[Column data for the given row]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>row4dat</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>ROW5DAT</name>
<description><![CDATA[Column data for the given row]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>row5dat</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>ROW6DAT</name>
<description><![CDATA[Column data for the given row]]></description>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>row6dat</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>ROW7DAT</name>
<description><![CDATA[Column data for the given row]]></description>
<addressOffset>0x0020</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>row7dat</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>ROW8DAT</name>
<description><![CDATA[Column data for the given row]]></description>
<addressOffset>0x0024</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>row8dat</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[Key injection request received]]></description>
<addressOffset>0x0028</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>keypressed</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``keypressed`` event]]></description>
</field>
<field>
<name>inject</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Level of the ``inject`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[Key injection request received]]></description>
<addressOffset>0x002c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>keypressed</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Triggered every time there is a difference in the row state]]></description>
</field>
<field>
<name>inject</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Key injection request received]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[Key injection request received]]></description>
<addressOffset>0x0030</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>keypressed</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``keypressed`` Event]]></description>
</field>
<field>
<name>inject</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Write a ``1`` to enable the ``inject`` Event]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x34</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>keyboard</name>
<value>13</value>
</interrupt>
</peripheral>
<peripheral>
<name>KEYINJECT</name>
<baseAddress>0xF0018000</baseAddress>
<groupName>KEYINJECT</groupName>
<registers>
<register>
<name>UART_CHAR</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>char</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[character value to inject. Automatically raises an interrupt upon write. There
is no interlock or FIFO buffering on this, so you can lose characters if you
inject too fast.]]></description>
</field>
<field>
<name>disable</name>
<msb>8</msb>
<bitRange>[8:8]</bitRange>
<lsb>8</lsb>
<description><![CDATA[writing a 1 permanently disables the block, until the next cold boot]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>SEED</name>
<baseAddress>0xF0019000</baseAddress>
<groupName>SEED</groupName>
<registers>
<register>
<name>SEED1</name>
<description><![CDATA[Bits 32-63 of `SEED_SEED`. Seed used for the build]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x4de9a155</resetValue>
<size>32</size>
<fields>
<field>
<name>seed</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>SEED0</name>
<description><![CDATA[Bits 0-31 of `SEED_SEED`.]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x35aac807</resetValue>
<size>32</size>
<fields>
<field>
<name>seed</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>KEYROM</name>
<baseAddress>0xF001A000</baseAddress>
<groupName>KEYROM</groupName>
<registers>
<register>
<name>ADDRESS</name>
<description><![CDATA[address for ROM]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>address</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DATA</name>
<description><![CDATA[data from ROM]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>data</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>LOCKADDR</name>
<description><![CDATA[address of the word to lock. Address locked on write, and cannot be undone.]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>lockaddr</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>LOCKSTAT</name>
<description><![CDATA[If set, the requested address word is locked and will always return 0.]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>lockstat</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>AUDIO</name>
<baseAddress>0xF001B000</baseAddress>
<groupName>AUDIO</groupName>
<registers>
<register>
<name>EV_STATUS</name>
<description><![CDATA[Indicates a Tx error has happened (over/underflow]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rx_ready</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``rx_ready`` event]]></description>
</field>
<field>
<name>rx_error</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Level of the ``rx_error`` event]]></description>
</field>
<field>
<name>tx_ready</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Level of the ``tx_ready`` event]]></description>
</field>
<field>
<name>tx_error</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[Level of the ``tx_error`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[Indicates a Tx error has happened (over/underflow]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rx_ready</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Indicates FIFO is ready to read]]></description>
</field>
<field>
<name>rx_error</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Indicates an Rx error has happened (over/underflow)]]></description>
</field>
<field>
<name>tx_ready</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Indicates enough space available for next Tx quanta of 256 words]]></description>
</field>
<field>
<name>tx_error</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[Indicates a Tx error has happened (over/underflow]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[Indicates a Tx error has happened (over/underflow]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rx_ready</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``rx_ready`` Event]]></description>
</field>
<field>
<name>rx_error</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Write a ``1`` to enable the ``rx_error`` Event]]></description>
</field>
<field>
<name>tx_ready</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Write a ``1`` to enable the ``tx_ready`` Event]]></description>
</field>
<field>
<name>tx_error</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[Write a ``1`` to enable the ``tx_error`` Event]]></description>
</field>
</fields>
</register>
<register>
<name>RX_CTL</name>
<description><![CDATA[Rx data path control]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>enable</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Enable the receiving data]]></description>
</field>
<field>
<name>reset</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Writing `1` resets the FIFO. Reset happens regardless of enable state.]]></description>
</field>
</fields>
</register>
<register>
<name>RX_STAT</name>
<description><![CDATA[Rx data path status]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x80000000</resetValue>
<size>32</size>
<fields>
<field>
<name>overflow</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Rx overflow]]></description>
</field>
<field>
<name>underflow</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Rx underflow]]></description>
</field>
<field>
<name>dataready</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[256 words of data loaded and ready to read]]></description>
</field>
<field>
<name>empty</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[No data available in FIFO to read]]></description>
</field>
<field>
<name>wrcount</name>
<msb>12</msb>
<bitRange>[12:4]</bitRange>
<lsb>4</lsb>
<description><![CDATA[Write count]]></description>
</field>
<field>
<name>rdcount</name>
<msb>21</msb>
<bitRange>[21:13]</bitRange>
<lsb>13</lsb>
<description><![CDATA[Read count]]></description>
</field>
<field>
<name>fifo_depth</name>
<msb>30</msb>
<bitRange>[30:22]</bitRange>
<lsb>22</lsb>
<description><![CDATA[FIFO depth as synthesized]]></description>
</field>
<field>
<name>concatenate_channels</name>
<msb>31</msb>
<bitRange>[31:31]</bitRange>
<lsb>31</lsb>
<description><![CDATA[Receive and send both channels atomically]]></description>
</field>
</fields>
</register>
<register>
<name>RX_CONF</name>
<description><![CDATA[Rx configuration]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0xac4441</resetValue>
<size>32</size>
<fields>
<field>
<name>format</name>
<msb>1</msb>
<bitRange>[1:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[I2S sample format. I2S_FORMAT.I2S_LEFT_JUSTIFIED is left-justified,
I2S_FORMAT.I2S_STANDARD is I2S standard]]></description>
</field>
<field>
<name>sample_width</name>
<msb>7</msb>
<bitRange>[7:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Single sample width]]></description>
</field>
<field>
<name>lrck_freq</name>
<msb>31</msb>
<bitRange>[31:8]</bitRange>
<lsb>8</lsb>
<description><![CDATA[Audio sampling rate frequency]]></description>
</field>
</fields>
</register>
<register>
<name>TX_CTL</name>
<description><![CDATA[Tx data path control]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>enable</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Enable the transmission data]]></description>
</field>
<field>
<name>reset</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Writing `1` resets the FIFO. Reset happens regardless of enable state.]]></description>
</field>
</fields>
</register>
<register>
<name>TX_STAT</name>
<description><![CDATA[Tx data path status]]></description>
<addressOffset>0x001c</addressOffset>
<resetValue>0x1000000</resetValue>
<size>32</size>
<fields>
<field>
<name>overflow</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Tx overflow]]></description>
</field>
<field>
<name>underflow</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Tx underflow]]></description>
</field>
<field>
<name>free</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[At least 256 words of space free]]></description>
</field>
<field>
<name>almostfull</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[Less than 8 words space available]]></description>
</field>
<field>
<name>full</name>
<msb>4</msb>
<bitRange>[4:4]</bitRange>
<lsb>4</lsb>
<description><![CDATA[FIFO is full or overfull]]></description>
</field>
<field>
<name>empty</name>
<msb>5</msb>
<bitRange>[5:5]</bitRange>
<lsb>5</lsb>
<description><![CDATA[FIFO is empty]]></description>
</field>
<field>
<name>wrcount</name>
<msb>14</msb>
<bitRange>[14:6]</bitRange>
<lsb>6</lsb>
<description><![CDATA[Tx write count]]></description>
</field>
<field>
<name>rdcount</name>
<msb>23</msb>
<bitRange>[23:15]</bitRange>
<lsb>15</lsb>
<description><![CDATA[Tx read count]]></description>
</field>
<field>
<name>concatenate_channels</name>
<msb>24</msb>
<bitRange>[24:24]</bitRange>
<lsb>24</lsb>
<description><![CDATA[Receive and send both channels atomically]]></description>
</field>
</fields>
</register>
<register>
<name>TX_CONF</name>
<description><![CDATA[TX configuration]]></description>
<addressOffset>0x0020</addressOffset>
<resetValue>0xac4441</resetValue>
<size>32</size>
<fields>
<field>
<name>format</name>
<msb>1</msb>
<bitRange>[1:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[I2S sample format. I2S_FORMAT.I2S_LEFT_JUSTIFIED is left-justified,
I2S_FORMAT.I2S_STANDARD is I2S standard]]></description>
</field>
<field>
<name>sample_width</name>
<msb>7</msb>
<bitRange>[7:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Single sample width]]></description>
</field>
<field>
<name>lrck_freq</name>
<msb>31</msb>
<bitRange>[31:8]</bitRange>
<lsb>8</lsb>
<description><![CDATA[Audio sampling rate frequency]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x24</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>audio</name>
<value>14</value>
</interrupt>
</peripheral>
<peripheral>
<name>TRNG_KERNEL</name>
<baseAddress>0xF001C000</baseAddress>
<groupName>TRNG_KERNEL</groupName>
<registers>
<register>
<name>STATUS</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ready</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[When set, indicates that the TRNG interface is capable of generating numbers]]></description>
</field>
<field>
<name>avail</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Indicates that the read FIFO is not empty]]></description>
</field>
<field>
<name>rdcount</name>
<msb>11</msb>
<bitRange>[11:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Read fifo pointer]]></description>
</field>
<field>
<name>wrcount</name>
<msb>21</msb>
<bitRange>[21:12]</bitRange>
<lsb>12</lsb>
<description><![CDATA[Write fifo pointer]]></description>
</field>
</fields>
</register>
<register>
<name>DATA</name>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>data</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[(DEPRECATED - use `urandom`) Latest random data from the FIFO; only valid if
``avail`` bit is set. This interface is preserved primarily for test programs to
access raw TRNG data, but normal kernel code should never use
this port, due to a race condition with the automatic reseeding algorithm for
urandom.]]></description>
</field>
</fields>
</register>
<register>
<name>URANDOM</name>
<description><![CDATA[Unlimited random numbers, output from the ChaCha conditioner. Generally, you
want to use this.]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>urandom</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>URANDOM_VALID</name>
<description><![CDATA[Set when `urandom` is valid. Always check before taking `urandom`]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>urandom_valid</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[Triggered whenever an underrun condition first occurs on the kernel interface]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>avail</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``avail`` event]]></description>
</field>
<field>
<name>error</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Level of the ``error`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[Triggered whenever an underrun condition first occurs on the kernel interface]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>avail</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Triggered anytime there is data available on the kernel interface]]></description>
</field>
<field>
<name>error</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Triggered whenever an underrun condition first occurs on the kernel interface]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[Triggered whenever an underrun condition first occurs on the kernel interface]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>avail</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``avail`` Event]]></description>
</field>
<field>
<name>error</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Write a ``1`` to enable the ``error`` Event]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x1c</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>trng_kernel</name>
<value>15</value>
</interrupt>
</peripheral>
<peripheral>
<name>TRNG_SERVER</name>
<baseAddress>0xF001D000</baseAddress>
<groupName>TRNG_SERVER</groupName>
<registers>
<register>
<name>CONTROL</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x09</resetValue>
<size>32</size>
<fields>
<field>
<name>enable</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Power on the management interface and auto-fill random numbers]]></description>
</field>
<field>
<name>ro_dis</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[When set, disables the ring oscillator as an entropy source]]></description>
</field>
<field>
<name>av_dis</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[When set, disables the avalanche generator as an entropy source]]></description>
</field>
<field>
<name>powersave</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[When set, TRNGs are automatically turned off until the low water mark is hit;
when cleared, TRNGs are always on]]></description>
</field>
<field>
<name>clr_err</name>
<msb>4</msb>
<bitRange>[4:4]</bitRange>
<lsb>4</lsb>
<description><![CDATA[Write ``1`` to this bit to clear the ``errors`` register]]></description>
</field>
</fields>
</register>
<register>
<name>DATA</name>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>data</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Latest random data from the FIFO; only valid if available bit is set Unlike the
kernel's raw data port, this one is safe to use as there is no race condition
with the reseeding algorithm. That being said, it is preferred to
use `urandom` because the Conditioner protects against unanticipated dropouts in
the raw TRNG stream.]]></description>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>avail</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[FIFO data is available]]></description>
</field>
<field>
<name>rdcount</name>
<msb>10</msb>
<bitRange>[10:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Read fifo pointer]]></description>
</field>
<field>
<name>wrcount</name>
<msb>20</msb>
<bitRange>[20:11]</bitRange>
<lsb>11</lsb>
<description><![CDATA[Write fifo pointer]]></description>
</field>
<field>
<name>full</name>
<msb>21</msb>
<bitRange>[21:21]</bitRange>
<lsb>21</lsb>
<description><![CDATA[Both kernel and server FIFOs have been topped off]]></description>
</field>
<field>
<name>chacha_ready</name>
<msb>22</msb>
<bitRange>[22:22]</bitRange>
<lsb>22</lsb>
<description><![CDATA[Chacha conditioner is seeded and ready]]></description>
</field>
</fields>
</register>
<register>
<name>AV_CONFIG</name>
<addressOffset>0x000c</addressOffset>
<resetValue>0x200c350</resetValue>
<size>32</size>
<fields>
<field>
<name>powerdelay</name>
<msb>19</msb>
<bitRange>[19:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Delay in microseconds for avalanche generator to stabilize]]></description>
</field>
<field>
<name>samples</name>
<msb>27</msb>
<bitRange>[27:20]</bitRange>
<lsb>20</lsb>
<description><![CDATA[Number of samples to fold into a single result. Smaller values increase rate but
decrease quality. Default is 32.]]></description>
</field>
<field>
<name>test</name>
<msb>28</msb>
<bitRange>[28:28]</bitRange>
<lsb>28</lsb>
<description><![CDATA[When set, puts the generator into test mode -- full-size, raw ADC samples are
directly placed into the FIFO at full rate, creating a 'virtual oscilloscope'
snapshot of the avalanche generator waveform.]]></description>
</field>
<field>
<name>required</name>
<msb>29</msb>
<bitRange>[29:29]</bitRange>
<lsb>29</lsb>
<description><![CDATA[Require avalanche generator to work in order for boot (used by the synthetic
test bench as this self-test 'runs long' compared to the other operations)]]></description>
</field>
</fields>
</register>
<register>
<name>RO_CONFIG</name>
<addressOffset>0x0010</addressOffset>
<resetValue>0x38080c9</resetValue>
<size>32</size>
<fields>
<field>
<name>gang</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Fold in collective gang entropy during dwell time]]></description>
</field>
<field>
<name>dwell</name>
<msb>12</msb>
<bitRange>[12:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Prescaler to set dwell-time of entropy collection. Controls the period of how
long the oscillators are in a metastable state to collect entropy before
sampling. Value encodes the number of sysclk edges to pass during the dwell
period.]]></description>
</field>
<field>
<name>delay</name>
<msb>22</msb>
<bitRange>[22:13]</bitRange>
<lsb>13</lsb>
<description><![CDATA[Sampler delay time. Sets the delay between when the small rings are merged
together, and when the final entropy result is sampled. Value encodes number of
sysclk edges to pass during the delay period. Delay should be long enough for
the signal to propagate around the merged ring, but longer times also means more
coupling of the deterministic sysclk noise into the rings.]]></description>
</field>
<field>
<name>fuzz</name>
<msb>23</msb>
<bitRange>[23:23]</bitRange>
<lsb>23</lsb>
<description><![CDATA[Modulate the `delay`/`dwell` parameter slightly from run-to-run, based on
previous run's random values. May help to break ring oscillator resonances
trained by the delay/dwell periodicity.]]></description>
</field>
<field>
<name>oversampling</name>
<msb>31</msb>
<bitRange>[31:24]</bitRange>
<lsb>24</lsb>
<description><![CDATA[Number of stages to oversample entropy. Normally, each bit is just sampled and
shifted once (so 32 times for 32-bit word). Each increment of oversampling will
add another stage.]]></description>
</field>
</fields>
</register>
<register>
<name>AV_NIST</name>
<addressOffset>0x0014</addressOffset>
<resetValue>0xcd29</resetValue>
<size>32</size>
<fields>
<field>
<name>repcount_cutoff</name>
<msb>6</msb>
<bitRange>[6:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Sets the `C` (cutoff) parameter in the NIST repetition count test for the
avalanche generator]]></description>
</field>
<field>
<name>adaptive_cutoff</name>
<msb>15</msb>
<bitRange>[15:7]</bitRange>
<lsb>7</lsb>
<description><![CDATA[Sets the `C` (cutoff) parameter in the NIST adaptive proportion test for the
avalanche generator]]></description>
</field>
</fields>
</register>
<register>
<name>RO_NIST</name>
<addressOffset>0x0018</addressOffset>
<resetValue>0x1a443</resetValue>
<size>32</size>
<fields>
<field>
<name>repcount_cutoff</name>
<msb>6</msb>
<bitRange>[6:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Sets the `C` (cutoff) parameter in the NIST repetition count test for the
ringosc generator]]></description>
</field>
<field>
<name>adaptive_cutoff</name>
<msb>16</msb>
<bitRange>[16:7]</bitRange>
<lsb>7</lsb>
<description><![CDATA[Sets the `C` (cutoff) parameter in the NIST adaptive proportion test for the
ringosg generator]]></description>
</field>
</fields>
</register>
<register>
<name>UNDERRUNS</name>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>server_underrun</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[If non-zero, a server underrun has occurred. Will count number of underruns up
to max field size]]></description>
</field>
<field>
<name>kernel_underrun</name>
<msb>19</msb>
<bitRange>[19:10]</bitRange>
<lsb>10</lsb>
<description><![CDATA[If non-zero, a kernel underrun has occurred. Will count number of underruns up
to max field size]]></description>
</field>
</fields>
</register>
<register>
<name>NIST_ERRORS</name>
<addressOffset>0x0020</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>av_repcount</name>
<msb>1</msb>
<bitRange>[1:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Indicates a failure in a repcount test for one of two avalanche generators]]></description>
</field>
<field>
<name>av_adaptive</name>
<msb>3</msb>
<bitRange>[3:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Indicates a failure in a adaptive proportion test for one of two avalanche
generators]]></description>
</field>
<field>
<name>ro_repcount</name>
<msb>7</msb>
<bitRange>[7:4]</bitRange>
<lsb>4</lsb>
<description><![CDATA[Indicates a failure in the repcount test for the ring oscillators]]></description>
</field>
<field>
<name>ro_adaptive</name>
<msb>11</msb>
<bitRange>[11:8]</bitRange>
<lsb>8</lsb>
<description><![CDATA[Indicates a failure in the adaptive proportion test for the ring oscillators]]></description>
</field>
<field>
<name>ro_miniruns</name>
<msb>15</msb>
<bitRange>[15:12]</bitRange>
<lsb>12</lsb>
<description><![CDATA[Indicates a failure in the miniruns test]]></description>
</field>
</fields>
</register>
<register>
<name>NIST_RO_STAT0</name>
<addressOffset>0x0024</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>adap_b</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[last window's `b` value for core 0 adaptive proportion test]]></description>
</field>
<field>
<name>fresh</name>
<msb>10</msb>
<bitRange>[10:10]</bitRange>
<lsb>10</lsb>
<description><![CDATA[when `1`, adaptive proprotion b has been updated since last read]]></description>
</field>
<field>
<name>rep_b</name>
<msb>17</msb>
<bitRange>[17:11]</bitRange>
<lsb>11</lsb>
<description><![CDATA[max `b` value for core 0 repetition count test]]></description>
</field>
</fields>
</register>
<register>
<name>NIST_RO_STAT1</name>
<addressOffset>0x0028</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>adap_b</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[last window's `b` value for core 1 adaptive proportion test]]></description>
</field>
<field>
<name>fresh</name>
<msb>10</msb>
<bitRange>[10:10]</bitRange>
<lsb>10</lsb>
<description><![CDATA[when `1`, adaptive proprotion b has been updated since last read]]></description>
</field>
<field>
<name>rep_b</name>
<msb>17</msb>
<bitRange>[17:11]</bitRange>
<lsb>11</lsb>
<description><![CDATA[max `b` value for core 0 repetition count test]]></description>
</field>
</fields>
</register>
<register>
<name>NIST_RO_STAT2</name>
<addressOffset>0x002c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>adap_b</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[last window's `b` value for core 2 adaptive proportion test]]></description>
</field>
<field>
<name>fresh</name>
<msb>10</msb>
<bitRange>[10:10]</bitRange>
<lsb>10</lsb>
<description><![CDATA[when `1`, adaptive proprotion b has been updated since last read]]></description>
</field>
<field>
<name>rep_b</name>
<msb>17</msb>
<bitRange>[17:11]</bitRange>
<lsb>11</lsb>
<description><![CDATA[max `b` value for core 0 repetition count test]]></description>
</field>
</fields>
</register>
<register>
<name>NIST_RO_STAT3</name>
<addressOffset>0x0030</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>adap_b</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[last window's `b` value for core 3 adaptive proportion test]]></description>
</field>
<field>
<name>fresh</name>
<msb>10</msb>
<bitRange>[10:10]</bitRange>
<lsb>10</lsb>
<description><![CDATA[when `1`, adaptive proprotion b has been updated since last read]]></description>
</field>
<field>
<name>rep_b</name>
<msb>17</msb>
<bitRange>[17:11]</bitRange>
<lsb>11</lsb>
<description><![CDATA[max `b` value for core 0 repetition count test]]></description>
</field>
</fields>
</register>
<register>
<name>NIST_AV_STAT0</name>
<addressOffset>0x0034</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>adap_b</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[last window's `b` value for core 0 adaptive proportion test]]></description>
</field>
<field>
<name>fresh</name>
<msb>10</msb>
<bitRange>[10:10]</bitRange>
<lsb>10</lsb>
<description><![CDATA[when `1`, adaptive proprotion b has been updated since last read]]></description>
</field>
<field>
<name>rep_b</name>
<msb>17</msb>
<bitRange>[17:11]</bitRange>
<lsb>11</lsb>
<description><![CDATA[max `b` value for core 0 repetition count test]]></description>
</field>
</fields>
</register>
<register>
<name>NIST_AV_STAT1</name>
<addressOffset>0x0038</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>adap_b</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[last window's `b` value for core 0 adaptive proportion test]]></description>
</field>
<field>
<name>fresh</name>
<msb>10</msb>
<bitRange>[10:10]</bitRange>
<lsb>10</lsb>
<description><![CDATA[when `1`, adaptive proprotion b has been updated since last read]]></description>
</field>
<field>
<name>rep_b</name>
<msb>17</msb>
<bitRange>[17:11]</bitRange>
<lsb>11</lsb>
<description><![CDATA[max `b` value for core 0 repetition count test]]></description>
</field>
</fields>
</register>
<register>
<name>RO_RUNSLIMIT1</name>
<addressOffset>0x003c</addressOffset>
<resetValue>0x1241b8</resetValue>
<size>32</size>
<fields>
<field>
<name>min</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Minimum runs limit for runs of length 1]]></description>
</field>
<field>
<name>max</name>
<msb>21</msb>
<bitRange>[21:11]</bitRange>
<lsb>11</lsb>
<description><![CDATA[Minimum runs limit for runs of length 1]]></description>
</field>
</fields>
</register>
<register>
<name>RO_RUNSLIMIT2</name>
<addressOffset>0x0040</addressOffset>
<resetValue>0x9f0c1</resetValue>
<size>32</size>
<fields>
<field>
<name>min</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Minimum runs limit for runs of length 2]]></description>
</field>
<field>
<name>max</name>
<msb>21</msb>
<bitRange>[21:11]</bitRange>
<lsb>11</lsb>
<description><![CDATA[Minimum runs limit for runs of length 2]]></description>
</field>
</fields>
</register>
<register>
<name>RO_RUNSLIMIT3</name>
<addressOffset>0x0044</addressOffset>
<resetValue>0x57850</resetValue>
<size>32</size>
<fields>
<field>
<name>min</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Minimum runs limit for runs of length 3]]></description>
</field>
<field>
<name>max</name>
<msb>21</msb>
<bitRange>[21:11]</bitRange>
<lsb>11</lsb>
<description><![CDATA[Minimum runs limit for runs of length 3]]></description>
</field>
</fields>
</register>
<register>
<name>RO_RUNSLIMIT4</name>
<addressOffset>0x0048</addressOffset>
<resetValue>0x3181d</resetValue>
<size>32</size>
<fields>
<field>
<name>min</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Minimum runs limit for runs of length 4]]></description>
</field>
<field>
<name>max</name>
<msb>21</msb>
<bitRange>[21:11]</bitRange>
<lsb>11</lsb>
<description><![CDATA[Minimum runs limit for runs of length 4]]></description>
</field>
</fields>
</register>
<register>
<name>RO_RUN0_CTRL</name>
<addressOffset>0x004c</addressOffset>
<resetValue>0x3ff</resetValue>
<size>32</size>
<fields>
<field>
<name>window</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Number of samples over which to measure. Must be less than 2047, or else
undefined behavior occurs]]></description>
</field>
</fields>
</register>
<register>
<name>RO_RUN0_FRESH</name>
<description><![CDATA[The current data corresponding to a runlength of (bitposition +1) has been
updated at least once since the last readout of any register]]></description>
<addressOffset>0x0050</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run0_fresh</name>
<msb>3</msb>
<bitRange>[3:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN0_COUNT1</name>
<description><![CDATA[Count of sequence length 1 runs seen in the past window]]></description>
<addressOffset>0x0054</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run0_count1</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN0_COUNT2</name>
<description><![CDATA[Count of sequence length 2 runs seen in the past window]]></description>
<addressOffset>0x0058</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run0_count2</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN0_COUNT3</name>
<description><![CDATA[Count of sequence length 3 runs seen in the past window]]></description>
<addressOffset>0x005c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run0_count3</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN0_COUNT4</name>
<description><![CDATA[Count of sequence length 4 runs seen in the past window]]></description>
<addressOffset>0x0060</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run0_count4</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN1_CTRL</name>
<addressOffset>0x0064</addressOffset>
<resetValue>0x3ff</resetValue>
<size>32</size>
<fields>
<field>
<name>window</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Number of samples over which to measure. Must be less than 2047, or else
undefined behavior occurs]]></description>
</field>
</fields>
</register>
<register>
<name>RO_RUN1_FRESH</name>
<description><![CDATA[The current data corresponding to a runlength of (bitposition +1) has been
updated at least once since the last readout of any register]]></description>
<addressOffset>0x0068</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run1_fresh</name>
<msb>3</msb>
<bitRange>[3:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN1_COUNT1</name>
<description><![CDATA[Count of sequence length 1 runs seen in the past window]]></description>
<addressOffset>0x006c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run1_count1</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN1_COUNT2</name>
<description><![CDATA[Count of sequence length 2 runs seen in the past window]]></description>
<addressOffset>0x0070</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run1_count2</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN1_COUNT3</name>
<description><![CDATA[Count of sequence length 3 runs seen in the past window]]></description>
<addressOffset>0x0074</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run1_count3</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN1_COUNT4</name>
<description><![CDATA[Count of sequence length 4 runs seen in the past window]]></description>
<addressOffset>0x0078</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run1_count4</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN2_CTRL</name>
<addressOffset>0x007c</addressOffset>
<resetValue>0x3ff</resetValue>
<size>32</size>
<fields>
<field>
<name>window</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Number of samples over which to measure. Must be less than 2047, or else
undefined behavior occurs]]></description>
</field>
</fields>
</register>
<register>
<name>RO_RUN2_FRESH</name>
<description><![CDATA[The current data corresponding to a runlength of (bitposition +1) has been
updated at least once since the last readout of any register]]></description>
<addressOffset>0x0080</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run2_fresh</name>
<msb>3</msb>
<bitRange>[3:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN2_COUNT1</name>
<description><![CDATA[Count of sequence length 1 runs seen in the past window]]></description>
<addressOffset>0x0084</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run2_count1</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN2_COUNT2</name>
<description><![CDATA[Count of sequence length 2 runs seen in the past window]]></description>
<addressOffset>0x0088</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run2_count2</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN2_COUNT3</name>
<description><![CDATA[Count of sequence length 3 runs seen in the past window]]></description>
<addressOffset>0x008c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run2_count3</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN2_COUNT4</name>
<description><![CDATA[Count of sequence length 4 runs seen in the past window]]></description>
<addressOffset>0x0090</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run2_count4</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN3_CTRL</name>
<addressOffset>0x0094</addressOffset>
<resetValue>0x3ff</resetValue>
<size>32</size>
<fields>
<field>
<name>window</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Number of samples over which to measure. Must be less than 2047, or else
undefined behavior occurs]]></description>
</field>
</fields>
</register>
<register>
<name>RO_RUN3_FRESH</name>
<description><![CDATA[The current data corresponding to a runlength of (bitposition +1) has been
updated at least once since the last readout of any register]]></description>
<addressOffset>0x0098</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run3_fresh</name>
<msb>3</msb>
<bitRange>[3:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN3_COUNT1</name>
<description><![CDATA[Count of sequence length 1 runs seen in the past window]]></description>
<addressOffset>0x009c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run3_count1</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN3_COUNT2</name>
<description><![CDATA[Count of sequence length 2 runs seen in the past window]]></description>
<addressOffset>0x00a0</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run3_count2</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN3_COUNT3</name>
<description><![CDATA[Count of sequence length 3 runs seen in the past window]]></description>
<addressOffset>0x00a4</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run3_count3</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RO_RUN3_COUNT4</name>
<description><![CDATA[Count of sequence length 4 runs seen in the past window]]></description>
<addressOffset>0x00a8</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ro_run3_count4</name>
<msb>10</msb>
<bitRange>[10:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>AV_EXCURSION0_CTRL</name>
<addressOffset>0x00ac</addressOffset>
<resetValue>0x190140</resetValue>
<size>32</size>
<fields>
<field>
<name>cutoff</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Minimum excursion required to pass]]></description>
</field>
<field>
<name>reset</name>
<msb>12</msb>
<bitRange>[12:12]</bitRange>
<lsb>12</lsb>
<description><![CDATA[Write `1` to reset the system, including any error flags]]></description>
</field>
<field>
<name>window</name>
<msb>31</msb>
<bitRange>[31:13]</bitRange>
<lsb>13</lsb>
<description><![CDATA[Number of samples over which to measure]]></description>
</field>
</fields>
</register>
<register>
<name>AV_EXCURSION0_STAT</name>
<addressOffset>0x00b0</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>min</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Minimum of last window]]></description>
</field>
<field>
<name>max</name>
<msb>23</msb>
<bitRange>[23:12]</bitRange>
<lsb>12</lsb>
<description><![CDATA[Maximum of last window]]></description>
</field>
</fields>
</register>
<register>
<name>AV_EXCURSION0_LAST_ERR</name>
<addressOffset>0x00b4</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>min</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Minimum of last error window]]></description>
</field>
<field>
<name>max</name>
<msb>23</msb>
<bitRange>[23:12]</bitRange>
<lsb>12</lsb>
<description><![CDATA[Maximum of last error window]]></description>
</field>
</fields>
</register>
<register>
<name>AV_EXCURSION1_CTRL</name>
<addressOffset>0x00b8</addressOffset>
<resetValue>0x190140</resetValue>
<size>32</size>
<fields>
<field>
<name>cutoff</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Minimum excursion required to pass]]></description>
</field>
<field>
<name>reset</name>
<msb>12</msb>
<bitRange>[12:12]</bitRange>
<lsb>12</lsb>
<description><![CDATA[Write `1` to reset the system, including any error flags]]></description>
</field>
<field>
<name>window</name>
<msb>31</msb>
<bitRange>[31:13]</bitRange>
<lsb>13</lsb>
<description><![CDATA[Number of samples over which to measure]]></description>
</field>
</fields>
</register>
<register>
<name>AV_EXCURSION1_STAT</name>
<addressOffset>0x00bc</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>min</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Minimum of last window]]></description>
</field>
<field>
<name>max</name>
<msb>23</msb>
<bitRange>[23:12]</bitRange>
<lsb>12</lsb>
<description><![CDATA[Maximum of last window]]></description>
</field>
</fields>
</register>
<register>
<name>AV_EXCURSION1_LAST_ERR</name>
<addressOffset>0x00c0</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>min</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Minimum of last error window]]></description>
</field>
<field>
<name>max</name>
<msb>23</msb>
<bitRange>[23:12]</bitRange>
<lsb>12</lsb>
<description><![CDATA[Maximum of last error window]]></description>
</field>
</fields>
</register>
<register>
<name>READY</name>
<addressOffset>0x00c4</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>av_excursion</name>
<msb>1</msb>
<bitRange>[1:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[ready bits from the excursion test]]></description>
</field>
<field>
<name>av_adaprop</name>
<msb>3</msb>
<bitRange>[3:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[ready bits from the adaptive proportion test]]></description>
</field>
<field>
<name>ro_adaprop</name>
<msb>7</msb>
<bitRange>[7:4]</bitRange>
<lsb>4</lsb>
<description><![CDATA[ready bits from the adaptive proportion test]]></description>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[Triggered by a failure in the avalanche generator core 1 on-line excursion test]]></description>
<addressOffset>0x00c8</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>avail</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``avail`` event]]></description>
</field>
<field>
<name>error</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Level of the ``error`` event]]></description>
</field>
<field>
<name>health</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Level of the ``health`` event]]></description>
</field>
<field>
<name>excursion0</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[Level of the ``excursion0`` event]]></description>
</field>
<field>
<name>excursion1</name>
<msb>4</msb>
<bitRange>[4:4]</bitRange>
<lsb>4</lsb>
<description><![CDATA[Level of the ``excursion1`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[Triggered by a failure in the avalanche generator core 1 on-line excursion test]]></description>
<addressOffset>0x00cc</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>avail</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Triggered anytime there is data available on the server interface]]></description>
</field>
<field>
<name>error</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Triggered whenever an error condition first occurs on the server interface]]></description>
</field>
<field>
<name>health</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Triggered whenever a health event first occurs]]></description>
</field>
<field>
<name>excursion0</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[Triggered by a failure in the avalanche generator core 0 on-line excursion test]]></description>
</field>
<field>
<name>excursion1</name>
<msb>4</msb>
<bitRange>[4:4]</bitRange>
<lsb>4</lsb>
<description><![CDATA[Triggered by a failure in the avalanche generator core 1 on-line excursion test]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[Triggered by a failure in the avalanche generator core 1 on-line excursion test]]></description>
<addressOffset>0x00d0</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>avail</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``avail`` Event]]></description>
</field>
<field>
<name>error</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Write a ``1`` to enable the ``error`` Event]]></description>
</field>
<field>
<name>health</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Write a ``1`` to enable the ``health`` Event]]></description>
</field>
<field>
<name>excursion0</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[Write a ``1`` to enable the ``excursion0`` Event]]></description>
</field>
<field>
<name>excursion1</name>
<msb>4</msb>
<bitRange>[4:4]</bitRange>
<lsb>4</lsb>
<description><![CDATA[Write a ``1`` to enable the ``excursion1`` Event]]></description>
</field>
</fields>
</register>
<register>
<name>CHACHA</name>
<addressOffset>0x00d4</addressOffset>
<resetValue>0x100c8002</resetValue>
<size>32</size>
<fields>
<field>
<name>reseed_interval</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[How many ChaCha blocks to generate before automatically rotating the key pool]]></description>
</field>
<field>
<name>selfmix_interval</name>
<msb>27</msb>
<bitRange>[27:12]</bitRange>
<lsb>12</lsb>
<description><![CDATA[How many sysclk cycles in between automatic round advancement (adjust to reduce
standby power)]]></description>
</field>
<field>
<name>selfmix_ena</name>
<msb>28</msb>
<bitRange>[28:28]</bitRange>
<lsb>28</lsb>
<description><![CDATA[Enable self mixing feature]]></description>
</field>
</fields>
</register>
<register>
<name>SEED</name>
<description><![CDATA[Extra data to be rotated into the seed pool. This is supplemental to the
automatically seeded TRNG data. Data is committed to the pool immediately upon
write.]]></description>
<addressOffset>0x00d8</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>seed</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>URANDOM</name>
<description><![CDATA[Unlimited random numbers, output from the ChaCha conditioner. Generally, you
want to use this.]]></description>
<addressOffset>0x00dc</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>urandom</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>URANDOM_VALID</name>
<description><![CDATA[Set when `urandom` is valid. Always check before taking `urandom`]]></description>
<addressOffset>0x00e0</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>urandom_valid</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>TEST</name>
<addressOffset>0x00e4</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>simultaneous</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Force a simultaneous advance of kernel/user urandom. Used to exercise a corner
case in testing. Not harmful in production, just wasteful.]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0xe8</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>trng_server</name>
<value>16</value>
</interrupt>
</peripheral>
<peripheral>
<name>TRNG</name>
<baseAddress>0xF001E000</baseAddress>
<groupName>TRNG</groupName>
<registers>
<register>
<name>XADC_TEMPERATURE</name>
<description><![CDATA[Raw Temperature value from XADC.
Temperature (C) = ``Value`` x 503.975 / 4096 - 273.15.]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_temperature</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_VCCINT</name>
<description><![CDATA[Raw VCCINT value from XADC.
VCCINT (V) = ``Value`` x 3 / 4096.]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_vccint</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_VCCAUX</name>
<description><![CDATA[Raw VCCAUX value from XADC.
VCCAUX (V) = ``Value`` x 3 / 4096.]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_vccaux</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_VCCBRAM</name>
<description><![CDATA[Raw VCCBRAM value from XADC.
VCCBRAM (V) = ``Value`` x 3 / 4096.]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_vccbram</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_VBUS</name>
<description><![CDATA[Raw VBUS value from XADC]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_vbus</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_USB_P</name>
<description><![CDATA[Voltage on USB_P pin]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_usb_p</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_USB_N</name>
<description><![CDATA[Voltage on USB_N pin]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_usb_n</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_NOISE0</name>
<description><![CDATA[Raw noise0]]></description>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_noise0</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_NOISE1</name>
<description><![CDATA[Raw noise1]]></description>
<addressOffset>0x0020</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_noise1</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_EOC</name>
<description><![CDATA[End of Convertion Status, ``1``: Convertion Done.]]></description>
<addressOffset>0x0024</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_eoc</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_EOS</name>
<description><![CDATA[End of Sequence Status, ``1``: Sequence Done.]]></description>
<addressOffset>0x0028</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_eos</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_GPIO5</name>
<description><![CDATA[GPIO5 value]]></description>
<addressOffset>0x002c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_gpio5</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_GPIO2</name>
<description><![CDATA[GPIO2 value]]></description>
<addressOffset>0x0030</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_gpio2</name>
<msb>11</msb>
<bitRange>[11:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_DRP_ENABLE</name>
<addressOffset>0x0034</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_drp_enable</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_DRP_READ</name>
<addressOffset>0x0038</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_drp_read</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_DRP_WRITE</name>
<addressOffset>0x003c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_drp_write</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_DRP_DRDY</name>
<addressOffset>0x0040</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_drp_drdy</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_DRP_ADR</name>
<addressOffset>0x0044</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_drp_adr</name>
<msb>6</msb>
<bitRange>[6:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_DRP_DAT_W</name>
<addressOffset>0x0048</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_drp_dat_w</name>
<msb>15</msb>
<bitRange>[15:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>XADC_DRP_DAT_R</name>
<addressOffset>0x004c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>xadc_drp_dat_r</name>
<msb>15</msb>
<bitRange>[15:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x50</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>SHA512</name>
<baseAddress>0xF001F000</baseAddress>
<groupName>SHA512</groupName>
<registers>
<register>
<name>POWER</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>on</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Writing `1` turns on the clocks to this block, `0` stops the clocks (for power
savings)]]></description>
</field>
</fields>
</register>
<register>
<name>CONFIG</name>
<description><![CDATA[Configuration register for the HMAC block]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>sha_en</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Enable the SHA512 core]]></description>
</field>
<field>
<name>endian_swap</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Swap the endianness on the input data]]></description>
</field>
<field>
<name>digest_swap</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Swap the endianness on the output digest]]></description>
</field>
<field>
<name>select_256</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[Select SHA512/256 IV constants when set to `1`]]></description>
</field>
<field>
<name>reset</name>
<msb>4</msb>
<bitRange>[4:4]</bitRange>
<lsb>4</lsb>
<description><![CDATA[Resets the hardware. Power must be on for this to take effect.]]></description>
</field>
</fields>
</register>
<register>
<name>COMMAND</name>
<description><![CDATA[Command register for the HMAC block]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>hash_start</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Writing a 1 indicates the beginning of hash data]]></description>
</field>
<field>
<name>hash_process</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Writing a 1 digests the hash data]]></description>
</field>
</fields>
</register>
<register>
<name>DIGEST01</name>
<description><![CDATA[Bits 32-63 of `SHA512_DIGEST0`. digest word 0]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>digest0</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DIGEST00</name>
<description><![CDATA[Bits 0-31 of `SHA512_DIGEST0`.]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>digest0</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DIGEST11</name>
<description><![CDATA[Bits 32-63 of `SHA512_DIGEST1`. digest word 1]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>digest1</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DIGEST10</name>
<description><![CDATA[Bits 0-31 of `SHA512_DIGEST1`.]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>digest1</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DIGEST21</name>
<description><![CDATA[Bits 32-63 of `SHA512_DIGEST2`. digest word 2]]></description>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>digest2</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DIGEST20</name>
<description><![CDATA[Bits 0-31 of `SHA512_DIGEST2`.]]></description>
<addressOffset>0x0020</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>digest2</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DIGEST31</name>
<description><![CDATA[Bits 32-63 of `SHA512_DIGEST3`. digest word 3]]></description>
<addressOffset>0x0024</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>digest3</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DIGEST30</name>
<description><![CDATA[Bits 0-31 of `SHA512_DIGEST3`.]]></description>
<addressOffset>0x0028</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>digest3</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DIGEST41</name>
<description><![CDATA[Bits 32-63 of `SHA512_DIGEST4`. digest word 4]]></description>
<addressOffset>0x002c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>digest4</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DIGEST40</name>
<description><![CDATA[Bits 0-31 of `SHA512_DIGEST4`.]]></description>
<addressOffset>0x0030</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>digest4</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DIGEST51</name>
<description><![CDATA[Bits 32-63 of `SHA512_DIGEST5`. digest word 5]]></description>
<addressOffset>0x0034</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>digest5</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DIGEST50</name>
<description><![CDATA[Bits 0-31 of `SHA512_DIGEST5`.]]></description>
<addressOffset>0x0038</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>digest5</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DIGEST61</name>
<description><![CDATA[Bits 32-63 of `SHA512_DIGEST6`. digest word 6]]></description>
<addressOffset>0x003c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>digest6</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DIGEST60</name>
<description><![CDATA[Bits 0-31 of `SHA512_DIGEST6`.]]></description>
<addressOffset>0x0040</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>digest6</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DIGEST71</name>
<description><![CDATA[Bits 32-63 of `SHA512_DIGEST7`. digest word 7]]></description>
<addressOffset>0x0044</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>digest7</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DIGEST70</name>
<description><![CDATA[Bits 0-31 of `SHA512_DIGEST7`.]]></description>
<addressOffset>0x0048</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>digest7</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>MSG_LENGTH1</name>
<description><![CDATA[Bits 32-63 of `SHA512_MSG_LENGTH`. Bottom 64 bits of length of digested message,
in bits]]></description>
<addressOffset>0x004c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>msg_length</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>MSG_LENGTH0</name>
<description><![CDATA[Bits 0-31 of `SHA512_MSG_LENGTH`.]]></description>
<addressOffset>0x0050</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>msg_length</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[SHA512 is done]]></description>
<addressOffset>0x0054</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>err_valid</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``err_valid`` event]]></description>
</field>
<field>
<name>fifo_full</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Level of the ``fifo_full`` event]]></description>
</field>
<field>
<name>sha512_done</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Level of the ``sha512_done`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[SHA512 is done]]></description>
<addressOffset>0x0058</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>err_valid</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Error flag was generated]]></description>
</field>
<field>
<name>fifo_full</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[FIFO is full]]></description>
</field>
<field>
<name>sha512_done</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[SHA512 is done]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[SHA512 is done]]></description>
<addressOffset>0x005c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>err_valid</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``err_valid`` Event]]></description>
</field>
<field>
<name>fifo_full</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Write a ``1`` to enable the ``fifo_full`` Event]]></description>
</field>
<field>
<name>sha512_done</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[Write a ``1`` to enable the ``sha512_done`` Event]]></description>
</field>
</fields>
</register>
<register>
<name>FIFO</name>
<description><![CDATA[FIFO status]]></description>
<addressOffset>0x0060</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>reset_status</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[when set, the block is undergoing a soft reset]]></description>
</field>
<field>
<name>read_count</name>
<msb>9</msb>
<bitRange>[9:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[read pointer]]></description>
</field>
<field>
<name>write_count</name>
<msb>18</msb>
<bitRange>[18:10]</bitRange>
<lsb>10</lsb>
<description><![CDATA[write pointer]]></description>
</field>
<field>
<name>read_error</name>
<msb>19</msb>
<bitRange>[19:19]</bitRange>
<lsb>19</lsb>
<description><![CDATA[read error occurred]]></description>
</field>
<field>
<name>write_error</name>
<msb>20</msb>
<bitRange>[20:20]</bitRange>
<lsb>20</lsb>
<description><![CDATA[write error occurred]]></description>
</field>
<field>
<name>almost_full</name>
<msb>21</msb>
<bitRange>[21:21]</bitRange>
<lsb>21</lsb>
<description><![CDATA[almost full]]></description>
</field>
<field>
<name>almost_empty</name>
<msb>22</msb>
<bitRange>[22:22]</bitRange>
<lsb>22</lsb>
<description><![CDATA[almost empty]]></description>
</field>
<field>
<name>running</name>
<msb>23</msb>
<bitRange>[23:23]</bitRange>
<lsb>23</lsb>
<description><![CDATA[hash engine is running and controls are locked out]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x64</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>sha512</name>
<value>17</value>
</interrupt>
</peripheral>
<peripheral>
<name>ENGINE</name>
<baseAddress>0xF0020000</baseAddress>
<groupName>ENGINE</groupName>
<registers>
<register>
<name>WINDOW</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>window</name>
<msb>3</msb>
<bitRange>[3:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Selects the current register window to use]]></description>
</field>
</fields>
</register>
<register>
<name>MPSTART</name>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>mpstart</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Where to start execution]]></description>
</field>
</fields>
</register>
<register>
<name>MPLEN</name>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>mplen</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Length of the current microcode program. Thus valid code must be in the range of
[mpstart, mpstart + mplen]]]></description>
</field>
</fields>
</register>
<register>
<name>CONTROL</name>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>go</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Writing to this puts the engine in `run` mode, and it will execute mplen
microcode instructions starting at mpstart]]></description>
</field>
</fields>
</register>
<register>
<name>MPRESUME</name>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>mpresume</name>
<msb>9</msb>
<bitRange>[9:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Where to resume execution after a pause]]></description>
</field>
</fields>
</register>
<register>
<name>POWER</name>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>on</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Writing `1` turns on the clocks to this block, `0` stops the clocks (for power
savings). The handling of the clock gate is in a different module, this is just
a flag to that block.]]></description>
</field>
<field>
<name>pause_req</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Writing a `1` to this block will pause execution at the next micro-op, and allow
for read-out of data from RF/microcode. Must check pause_gnt to confirm the
pause has happened. Used to interrupt flow for suspend/resume.]]></description>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>running</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[When set, the microcode engine is running. All wishbone access to RF and
microcode memory areas will stall until this bit is clear]]></description>
</field>
<field>
<name>mpc</name>
<msb>10</msb>
<bitRange>[10:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Current location of the microcode program counter. Mostly for debug.]]></description>
</field>
<field>
<name>pause_gnt</name>
<msb>11</msb>
<bitRange>[11:11]</bitRange>
<lsb>11</lsb>
<description><![CDATA[When set, the engine execution has been paused, and the RF & microcode ROM can
be read out for suspend/resume]]></description>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[Illegal opcode encountered]]></description>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>finished</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``finished`` event]]></description>
</field>
<field>
<name>illegal_opcode</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Level of the ``illegal_opcode`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[Illegal opcode encountered]]></description>
<addressOffset>0x0020</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>finished</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Microcode run finished execution]]></description>
</field>
<field>
<name>illegal_opcode</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Illegal opcode encountered]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[Illegal opcode encountered]]></description>
<addressOffset>0x0024</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>finished</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``finished`` Event]]></description>
</field>
<field>
<name>illegal_opcode</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Write a ``1`` to enable the ``illegal_opcode`` Event]]></description>
</field>
</fields>
</register>
<register>
<name>INSTRUCTION</name>
<description><![CDATA[Current instruction being executed by the engine. The format of this register
exactly reflects the binary layout of an Engine instruction.]]></description>
<addressOffset>0x0028</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>opcode</name>
<msb>5</msb>
<bitRange>[5:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[opcode to be executed]]></description>
</field>
<field>
<name>ra</name>
<msb>10</msb>
<bitRange>[10:6]</bitRange>
<lsb>6</lsb>
<description><![CDATA[operand A read register]]></description>
</field>
<field>
<name>ca</name>
<msb>11</msb>
<bitRange>[11:11]</bitRange>
<lsb>11</lsb>
<description><![CDATA[set to substitute constant table value for A]]></description>
</field>
<field>
<name>rb</name>
<msb>16</msb>
<bitRange>[16:12]</bitRange>
<lsb>12</lsb>
<description><![CDATA[operand B read register]]></description>
</field>
<field>
<name>cb</name>
<msb>17</msb>
<bitRange>[17:17]</bitRange>
<lsb>17</lsb>
<description><![CDATA[set to substitute constant table value for B]]></description>
</field>
<field>
<name>wd</name>
<msb>22</msb>
<bitRange>[22:18]</bitRange>
<lsb>18</lsb>
<description><![CDATA[write register]]></description>
</field>
<field>
<name>immediate</name>
<msb>31</msb>
<bitRange>[31:23]</bitRange>
<lsb>23</lsb>
<description><![CDATA[Used by jumps to load the next PC value]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x2c</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>engine</name>
<value>18</value>
</interrupt>
</peripheral>
<peripheral>
<name>JTAG</name>
<baseAddress>0xF0021000</baseAddress>
<groupName>JTAG</groupName>
<registers>
<register>
<name>NEXT</name>
<description><![CDATA[Next state for TDI/TMS; writing automatically clocks TCK]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>tdi</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[TDI pin value]]></description>
</field>
<field>
<name>tms</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[TMS pin value]]></description>
</field>
</fields>
</register>
<register>
<name>TDO</name>
<description><![CDATA[TDO resulting from previous cycle]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>tdo</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[TDO pin value]]></description>
</field>
<field>
<name>ready</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[JTAG machine is ready for a new cycle; also indicates TDO is valid]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>WDT</name>
<baseAddress>0xF0022000</baseAddress>
<groupName>WDT</groupName>
<registers>
<register>
<name>WATCHDOG</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>reset_wdt</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write to this register to reset the watchdog timer]]></description>
</field>
<field>
<name>enable</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Enable the watchdog timer. Cannot be disabled once enabled, except with a reset.
Notably, a watchdog reset will disable the watchdog.]]></description>
</field>
</fields>
</register>
<register>
<name>PERIOD</name>
<addressOffset>0x0004</addressOffset>
<resetValue>0x135f1b40</resetValue>
<size>32</size>
<fields>
<field>
<name>period</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Number of 'approximately 65MHz' CFGMCLK cycles before each reset_code must be
entered. Defaults to a range of 1.67-5.00 seconds]]></description>
</field>
</fields>
</register>
<register>
<name>STATE</name>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>enabled</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[WDT has been enabled]]></description>
</field>
<field>
<name>armed1</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[WDT in the armed1 state]]></description>
</field>
<field>
<name>armed2</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[WDT in the armed2 state]]></description>
</field>
<field>
<name>disarmed</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[WDT in the disarmed state]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0xc</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>D11CTIME</name>
<baseAddress>0xF0023000</baseAddress>
<groupName>D11CTIME</groupName>
<registers>
<register>
<name>CONTROL</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x666</resetValue>
<size>32</size>
<fields>
<field>
<name>count</name>
<msb>14</msb>
<bitRange>[14:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Number of 1/32768 second ticks before creating a heart beat]]></description>
</field>
</fields>
</register>
<register>
<name>HEARTBEAT</name>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>beat</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Set to `1` at the next `count` interval rollover since `clear` was set.]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>WFI</name>
<baseAddress>0xF0024000</baseAddress>
<groupName>WFI</groupName>
<registers>
<register>
<name>WFI</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>wfi</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Writing a `1` triggers an attempt to sleep clocks until an event happens]]></description>
</field>
</fields>
</register>
<register>
<name>IGNORE_LOCKED</name>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>ignore_locked</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Writing a `1` causes the reset condition for the SoC to ignore the locked state
of the PLL]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>IDENTIFIER_MEM</name>
<baseAddress>0xF0025000</baseAddress>
<groupName>IDENTIFIER_MEM</groupName>
<registers>
<register>
<name>IDENTIFIER_MEM</name>
<description><![CDATA[8 x 19-bit memory]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>identifier_mem</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
</peripherals>
<vendorExtensions>
<memoryRegions>
<memoryRegion>
<name>ROM</name>
<baseAddress>0x80000000</baseAddress>
<size>0x00010000</size>
</memoryRegion>
<memoryRegion>
<name>VEXRISCV_DEBUG</name>
<baseAddress>0xEFFF0000</baseAddress>
<size>0x00000100</size>
</memoryRegion>
<memoryRegion>
<name>SRAM_EXT</name>
<baseAddress>0x40000000</baseAddress>
<size>0x01000000</size>
</memoryRegion>
<memoryRegion>
<name>MEMLCD</name>
<baseAddress>0xB0000000</baseAddress>
<size>0x00005C20</size>
</memoryRegion>
<memoryRegion>
<name>SPIFLASH</name>
<baseAddress>0x20000000</baseAddress>
<size>0x08000000</size>
</memoryRegion>
<memoryRegion>
<name>AUDIO</name>
<baseAddress>0xE0000000</baseAddress>
<size>0x00000004</size>
</memoryRegion>
<memoryRegion>
<name>SHA512</name>
<baseAddress>0xE0002000</baseAddress>
<size>0x00000004</size>
</memoryRegion>
<memoryRegion>
<name>ENGINE</name>
<baseAddress>0xE0020000</baseAddress>
<size>0x00020000</size>
</memoryRegion>
<memoryRegion>
<name>CSR</name>
<baseAddress>0xF0000000</baseAddress>
<size>0x00040000</size>
</memoryRegion>
</memoryRegions>
<constants>
<constant name="CONFIG_CLOCK_FREQUENCY" value="100000000" />
<constant name="CONFIG_CPU_HAS_INTERRUPT" value="None" />
<constant name="CONFIG_CPU_RESET_ADDR" value="2147483648" />
<constant name="CONFIG_CPU_TYPE_VEXRISCV" value="None" />
<constant name="CONFIG_CPU_VARIANT_STANDARD" value="None" />
<constant name="CONFIG_CPU_HUMAN_NAME" value="VexRiscv" />
<constant name="CONFIG_CPU_NOP" value="nop" />
<constant name="CONFIG_CSR_DATA_WIDTH" value="32" />
<constant name="CONFIG_CSR_ALIGNMENT" value="32" />
<constant name="CONFIG_BUS_STANDARD" value="WISHBONE" />
<constant name="CONFIG_BUS_DATA_WIDTH" value="32" />
<constant name="CONFIG_BUS_ADDRESS_WIDTH" value="32" />
<constant name="APP_UART_INTERRUPT" value="4" />
<constant name="AUDIO_INTERRUPT" value="14" />
<constant name="BTEVENTS_INTERRUPT" value="7" />
<constant name="COM_INTERRUPT" value="5" />
<constant name="CONSOLE_INTERRUPT" value="3" />
<constant name="ENGINE_INTERRUPT" value="18" />
<constant name="GPIO_INTERRUPT" value="1" />
<constant name="I2C_INTERRUPT" value="6" />
<constant name="KEYBOARD_INTERRUPT" value="13" />
<constant name="POWER_INTERRUPT" value="10" />
<constant name="SHA512_INTERRUPT" value="17" />
<constant name="SPINOR_INTERRUPT" value="12" />
<constant name="SPINOR_SOFT_INT_INTERRUPT" value="11" />
<constant name="SUSRES_INTERRUPT" value="9" />
<constant name="TICKTIMER_INTERRUPT" value="8" />
<constant name="TIMER0_INTERRUPT" value="0" />
<constant name="TRNG_KERNEL_INTERRUPT" value="15" />
<constant name="TRNG_SERVER_INTERRUPT" value="16" />
<constant name="UART_INTERRUPT" value="2" />
</constants>
</vendorExtensions>
</device>
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