mirror of https://github.com/saymrwulf/xous-core.git synced 2026-11-04 04:27:34 +00:00

History

bunnie 659796916a chore: cleanup typos in docs, comments		2024-01-15 02:16:43 +08:00
..
bbram-test1.jtg	jtag script for burning the key	2021-08-04 13:57:09 +08:00
bbram-test1.nky	add the test key for self-provisioning testing	2021-08-04 13:54:11 +08:00
long_8khz.wav	rename as generics	2021-05-02 18:11:31 +08:00
midwinter_original.wav	add audio samples for testing + credits	2021-05-02 18:04:13 +08:00
README.md	chore: cleanup typos in docs, comments	2024-01-15 02:16:43 +08:00
rom.db	absorb v0.9.10 soc artifacts	2022-10-09 17:53:12 +08:00
short_8khz.wav	rename as generics	2021-05-02 18:11:31 +08:00
short_cd.wav	rename as generics	2021-05-02 18:11:31 +08:00
soc_csr_dvt.bin	these were supposed to be renamed, not deleted	2023-03-08 03:47:36 +08:00
soc_csr_perf.bin	these were supposed to be renamed, not deleted	2023-03-08 03:47:36 +08:00
soc_csr_pvt.bin	update local SoC binary to track release	2023-08-08 14:31:27 +08:00
update_soc_pvt.sh	add a helper script to pull the SoC from CI	2023-03-10 00:03:20 +08:00

README.md

Audio Samples

The .wav files included here are meant for audio testing only and are intended to be bundled into the final distribution. Developers who want to use this for testing will need to manually stage and load these samples into the correct location in the FLASH. See https://github.com/betrusted-io/xous-core/blob/master/docs/flash.md for the locations of the samples.

tools/usb_update.py can provision the "long_8khz.wav" sample that is used by the latest demo of audio playback in xous-core.

The track samples included here are from "Midwinter", by Jackalope (https://soundcloud.com/tokyojackalope)

Used with permission to redistribute as part of this repository.

SoC Prebuild

A copy of a pre-built FPGA SoC binary that matches the latest version of the current tree is also included here. It's recommended to flash this pre-build FPGA image so your kernel matches the hardware if you're only building the kernel from scratch, and not also building the FPGA hardware.