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The "main" product line is affected here in that the UART init is hosted above the trng init. This should have no impact on security or boot time, but allows us to more easily debug TRNG init issues. This is necessary because in the vexii test version the XADC interface is broken by the slower clocking and I'm not taking the time to trace down that issue as it does nothing to further the goal of testing the vex-ii core in a non-production config. legacy_int handler allows vex-ii to emulate/behave like the vex-i in terms of interrupt handling. eventually this will be replaced with/augmeted by a PLIC. |
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| .. | ||
| arch | ||
| debug | ||
| platform | ||
| args.rs | ||
| io.rs | ||
| irq.rs | ||
| macros.rs | ||
| main.rs | ||
| mem.rs | ||
| server.rs | ||
| services.rs | ||
| swap.rs | ||
| syscall.rs | ||
| test.rs | ||
| utils.rs | ||