mirror of
https://github.com/saymrwulf/xous-core.git
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dc097e32d8
Atomic operations were previously broken. RISC-V breaks atomic operations into multiple instructions, and there is some state kept between those instructions. This state is not visible, and is internal to the processor. We were ignoring this state, which resulted in inconsistencies throughout the system. The following sequence was possible: 1. A thread loads a value, and obtains the `reservation set` 2. A context switch happens on the following instruction 3. A different thread loads the value, modifies it, and continues 4. A third thread (or a different process) loads a value and obtains the `reservation set` 5. The original thread runs, sees the `reservation set` is held, and updates the value, clobbering what the second thread did in #3 A workaround for this is to perform a dummy `sc` as part of the context switch. This invalidates any atomic operations that may be pending. Signed-off-by: Sean Cross <sean@xobs.io>
297 lines
9 KiB
ArmAsm
297 lines
9 KiB
ArmAsm
#if __riscv_xlen == 64
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# define STORE sd
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# define LOAD ld
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# define LOG_REGBYTES 3
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#else
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# define STORE sw
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# define LOAD lw
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# define LOG_REGBYTES 2
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#endif
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#define REGBYTES (1 << LOG_REGBYTES)
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/*
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Entry point of all programs (_start).
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It initializes DWARF call frame information, the stack pointer, the
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frame pointer (needed for closures to work in start_rust) and the global
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pointer. Then it calls _start_rust.
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*/
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.section .text.init, "ax"
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.global _start
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_start:
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// Set trap handler, which will be called
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// on interrupts and cpu faults
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la t0, _start_trap
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csrw stvec, t0
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/////// resume prep code
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// if resume flag is false (0), skip this section
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beq a7, zero, coldboot
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/*
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This is the resume code. The overall strategy is to have a suspend/resume cycle
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occur within an interrupt context. Thus, at this point of the suspend/resume
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cycle (e.g. the resume half), our strategy is to restore a minimal environment which
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allows a Xous interrupt context to run, which allows the Xous return-from-interrupt
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handler to set up the remainder of the resume tasks.
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*/
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// Restore a default stack pointer - used by interrupt handlers and considered temporary/smashable
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li sp, 0xfffefffc
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// setup sie [ssoft, sext]. This corresponds to bits 1 and 9, or 0b10_0000_0010
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li t0, 0x202
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csrw sie, t0
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// restore the SIM with the value previously socked away by the interrupt handler routine during the suspend half
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jal ra, _enable_all_irqs
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// set scause to simulate an interrupt's occurence -- this makes the resume "feel like" an interrupt
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// vectored into the same routine that caused the suspend, but without having gone through the typical
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// interrupt handler mechanisms
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li t0, 0x80000000
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csrw scause, t0
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// this is the same path the suspend interrupt took, but we set it up manually
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// and the loader had flipped the "resume" bit, so this should bring us into the resume branch.
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j _start_trap_rust
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coldboot:
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// Note that registers $a0-$a7 still contain the kernel arguments
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// Jump to a program to initialize global variables.
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// Note that at this point, the .data section should
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// have already been set up by the loader.
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jal x1, init
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// Call the kmain function. This function diverges, so
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// shouldn't ever return.
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j kmain
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/*
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Trap entry point (_start_trap)
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Saves all process context into a structure that is
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mapped to each thread at 0xff801000. Return happens
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elsewhere.
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*/
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.section .trap, "ax"
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.global _start_trap
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_start_trap:
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csrw sscratch, sp
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li sp, 0xff801000
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STORE x1, 0*REGBYTES(sp) // Store x1 in the scratch field
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LOAD x1, 1*REGBYTES(sp) // Load current context number
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slli x1, x1, 7 // Multiply current context number by 32
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add sp, sp, x1 // Set $sp to 0xff801000 + (current_context * 32)
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STORE x1, 0*REGBYTES(sp)
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// Skip SP for now
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STORE x3, 2*REGBYTES(sp)
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STORE x4, 3*REGBYTES(sp)
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STORE x5, 4*REGBYTES(sp)
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STORE x6, 5*REGBYTES(sp)
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STORE x7, 6*REGBYTES(sp)
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STORE x8, 7*REGBYTES(sp)
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STORE x9, 8*REGBYTES(sp)
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STORE x10, 9*REGBYTES(sp)
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STORE x11, 10*REGBYTES(sp)
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STORE x12, 11*REGBYTES(sp)
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STORE x13, 12*REGBYTES(sp)
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STORE x14, 13*REGBYTES(sp)
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STORE x15, 14*REGBYTES(sp)
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STORE x16, 15*REGBYTES(sp)
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STORE x17, 16*REGBYTES(sp)
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STORE x18, 17*REGBYTES(sp)
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STORE x19, 18*REGBYTES(sp)
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STORE x20, 19*REGBYTES(sp)
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STORE x21, 20*REGBYTES(sp)
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STORE x22, 21*REGBYTES(sp)
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STORE x23, 22*REGBYTES(sp)
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STORE x24, 23*REGBYTES(sp)
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STORE x25, 24*REGBYTES(sp)
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STORE x26, 25*REGBYTES(sp)
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STORE x27, 26*REGBYTES(sp)
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STORE x28, 27*REGBYTES(sp)
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STORE x29, 28*REGBYTES(sp)
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STORE x30, 29*REGBYTES(sp)
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STORE x31, 30*REGBYTES(sp)
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// Save SEPC
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csrr t0, sepc
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STORE t0, 31*REGBYTES(sp)
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// Save x1, which was used to calculate the offset. Prior to
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// calculating, it was stashed at 0xff801000.
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li t0, 0xff801000
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LOAD t1, 0*REGBYTES(t0)
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STORE t1, 0*REGBYTES(sp)
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// Finally, save SP
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csrr t0, sscratch
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STORE t0, 1*REGBYTES(sp)
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// Restore a default stack pointer
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li sp, 0xfffefffc
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// Note that registers $a0-$a7 still contain the arguments
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j _start_trap_rust
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/*
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Resume a context (_xous_resume_context)
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Restores all registers from a Context passed in $a0.
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Note that the SEPC and SSTATUS should be set already.
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*/
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.global _xous_resume_context
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_xous_resume_context:
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move sp, a0
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LOAD x1, 0*REGBYTES(sp)
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// Clear any reservations, invalidating any atomic operations
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#ifndef SKIP_MULTICORE
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sc.w zero, x1, 0*REGBYTES(sp)
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#endif
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// Skip SP for now
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LOAD x3, 2*REGBYTES(sp)
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LOAD x4, 3*REGBYTES(sp)
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LOAD x5, 4*REGBYTES(sp)
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LOAD x6, 5*REGBYTES(sp)
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LOAD x7, 6*REGBYTES(sp)
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LOAD x8, 7*REGBYTES(sp)
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LOAD x9, 8*REGBYTES(sp)
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LOAD x10, 9*REGBYTES(sp)
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LOAD x11, 10*REGBYTES(sp)
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LOAD x12, 11*REGBYTES(sp)
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LOAD x13, 12*REGBYTES(sp)
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LOAD x14, 13*REGBYTES(sp)
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LOAD x15, 14*REGBYTES(sp)
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LOAD x16, 15*REGBYTES(sp)
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LOAD x17, 16*REGBYTES(sp)
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LOAD x18, 17*REGBYTES(sp)
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LOAD x19, 18*REGBYTES(sp)
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LOAD x20, 19*REGBYTES(sp)
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LOAD x21, 20*REGBYTES(sp)
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LOAD x22, 21*REGBYTES(sp)
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LOAD x23, 22*REGBYTES(sp)
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LOAD x24, 23*REGBYTES(sp)
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LOAD x25, 24*REGBYTES(sp)
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LOAD x26, 25*REGBYTES(sp)
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LOAD x27, 26*REGBYTES(sp)
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LOAD x28, 27*REGBYTES(sp)
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LOAD x29, 28*REGBYTES(sp)
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LOAD x30, 29*REGBYTES(sp)
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LOAD x31, 30*REGBYTES(sp)
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// Restore SP
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LOAD x2, 1*REGBYTES(sp)
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sret
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/*
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Return from a syscall with arguments (_xous_syscall_return_result)
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Xous passes arguments in $a0-$a7, however the RISC-V calling convention
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states that only $a0 and $a1 are used. To work around this, we pass
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a pointer to a 32-byte structure in $a0, and this function moves that
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into the registers. It then restores the context from other registers.
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*/
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.global _xous_syscall_return_result
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_xous_syscall_return_result:
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move sp, a1
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LOAD t0, 31*REGBYTES(sp)
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csrw sepc, t0
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LOAD x1, 0*REGBYTES(sp)
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// An atomic operation is broken up into multiple instructions.
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// A program first issues a `lr` instruction, which basically
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// raises a flag saying that an atomic operation is now live. It
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// then issues an `sc` instruction, and if the flag is still held
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// it succeeds and clears the flag.
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//
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// This flag is a bit of state within the processor, and the
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// RISC-V spec doesn't say how to access it. However, it is only
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// one bit, and we can clear the bit by performing a dummy `sc`
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// here. This will cause a failure in any atomic operation in the
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// program we're switching to.
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#ifndef SKIP_MULTICORE
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sc.w zero, x1, 0*REGBYTES(sp)
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#endif
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// Skip SP for now
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LOAD x3, 2*REGBYTES(sp)
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LOAD x4, 3*REGBYTES(sp)
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LOAD x5, 4*REGBYTES(sp)
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LOAD x6, 5*REGBYTES(sp)
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LOAD x7, 6*REGBYTES(sp)
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LOAD x8, 7*REGBYTES(sp)
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LOAD x9, 8*REGBYTES(sp)
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// Load argument registers from the value pointed
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// to by $a0
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LOAD a7, 7*REGBYTES(a0)
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LOAD a6, 6*REGBYTES(a0)
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LOAD a5, 5*REGBYTES(a0)
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LOAD a4, 4*REGBYTES(a0)
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LOAD a3, 3*REGBYTES(a0)
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LOAD a2, 2*REGBYTES(a0)
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LOAD a1, 1*REGBYTES(a0)
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LOAD a0, 0*REGBYTES(a0)
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LOAD x18, 17*REGBYTES(sp)
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LOAD x19, 18*REGBYTES(sp)
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LOAD x20, 19*REGBYTES(sp)
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LOAD x21, 20*REGBYTES(sp)
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LOAD x22, 21*REGBYTES(sp)
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LOAD x23, 22*REGBYTES(sp)
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LOAD x24, 23*REGBYTES(sp)
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LOAD x25, 24*REGBYTES(sp)
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LOAD x26, 25*REGBYTES(sp)
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LOAD x27, 26*REGBYTES(sp)
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LOAD x28, 27*REGBYTES(sp)
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LOAD x29, 28*REGBYTES(sp)
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LOAD x30, 29*REGBYTES(sp)
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LOAD x31, 30*REGBYTES(sp)
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// Restore SP
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//csrr t0, sscratch
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LOAD x2, 1*REGBYTES(sp)
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sret
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.global flush_mmu
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flush_mmu:
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sfence.vma
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ret
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/*
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Endcap of valid RISC-V code, to ensure speculative reads
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past the end of the .text section to not trigger an illegal
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instuction opcode. This cap is equal to the width of a cache line,
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using the 2-byte RV32C encoding.
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*/
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.section .endcap, "ax"
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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