mirror of
https://github.com/saymrwulf/xous-core.git
synced 2026-11-12 07:44:18 +00:00
9cfffb18e9
there is still some mysterious problem involving a race condition of the raw hardware console UART Rx path deciding it doesn't want to report new characters anymore to the interrupt handler that is triggered when multi-byte sequences are shoved down the pipe. So long as you're typing simple commands it's fine, but escape sequences tend to lock things up. I don't think there's enough ROI to continue investigating this facility.
112 lines
3 KiB
Rust
112 lines
3 KiB
Rust
use core::fmt::{Error, Write};
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use utralib::generated::*;
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#[macro_export]
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macro_rules! print
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{
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($($args:tt)+) => ({
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use core::fmt::Write;
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let _ = write!(crate::debug::Uart {}, $($args)+);
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});
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}
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#[macro_export]
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macro_rules! println
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{
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() => ({
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print!("\r\n")
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});
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($fmt:expr) => ({
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print!(concat!($fmt, "\r\n"))
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});
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($fmt:expr, $($args:tt)+) => ({
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print!(concat!($fmt, "\r\n"), $($args)+)
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});
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}
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#[allow(dead_code)]
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fn handle_irq(irq_no: usize, arg: *mut usize) {
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print!("Handling IRQ {} (arg: {:08x}): ", irq_no, arg as usize);
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while let Some(c) = { crate::debug::Uart {} }.getc() {
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print!("{}", c as char);
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}
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println!();
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}
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pub struct Uart {}
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// this is a hack to bypass an explicit initialization/allocation step for the debug structure
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pub static mut DEFAULT_UART_ADDR: *mut usize = 0x0000_0000 as *mut usize;
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pub const DEFAULT: Uart = Uart {};
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impl Uart {
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fn map_uart(&self) {
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/*
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Note: the memory address and interrupt specified here needs to map to a unique hardware
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UART resource. Modify in this function as necessary.
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*/
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let uart = xous::syscall::map_memory(
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xous::MemoryAddress::new(utra::console::HW_CONSOLE_BASE),
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None,
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4096,
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xous::MemoryFlags::R | xous::MemoryFlags::W,
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)
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.expect("couldn't map debug uart");
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unsafe {
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DEFAULT_UART_ADDR = uart.as_mut_ptr() as _;
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}
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println!("Mapped UART @ {:08x}", uart.as_ptr() as usize);
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// core::mem::forget(uart);
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println!("Allocating IRQ...");
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/* xous::claim_interrupt(
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utra::console::CONSOLE_IRQ,
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handle_irq,
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core::ptr::null_mut::<usize>(),
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)
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.expect("unable to allocate IRQ"); */
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self.enable_rx();
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}
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pub fn putc(&self, c: u8) {
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if unsafe { DEFAULT_UART_ADDR } as usize == 0 {
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self.map_uart();
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}
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let mut uart_csr = CSR::new(unsafe { DEFAULT_UART_ADDR as *mut u32 });
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// Wait until TXFULL is `0`
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while uart_csr.r(utra::uart::TXFULL) != 0 {}
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uart_csr.wo(utra::uart::RXTX, c as u32);
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}
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pub fn enable_rx(&self) {
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let mut uart_csr = CSR::new(unsafe { DEFAULT_UART_ADDR as *mut u32 });
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uart_csr.rmwf(utra::uart::EV_ENABLE_RX, 1);
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}
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#[allow(dead_code)]
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pub fn getc(&self) -> Option<u8> {
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if unsafe { DEFAULT_UART_ADDR } as usize == 0 {
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self.map_uart();
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}
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let mut uart_csr = CSR::new(unsafe { DEFAULT_UART_ADDR as *mut u32 });
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match uart_csr.rf(utra::uart::EV_PENDING_RX) {
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0 => None,
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ack => {
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let c = Some(uart_csr.rf(utra::uart::RXTX_RXTX) as u8);
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uart_csr.wfo(utra::uart::EV_PENDING_RX, ack);
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c
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}
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}
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}
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}
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impl Write for Uart {
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fn write_str(&mut self, s: &str) -> Result<(), Error> {
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for c in s.bytes() {
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self.putc(c);
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}
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Ok(())
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}
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}
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