mirror of
https://github.com/saymrwulf/xous-core.git
synced 2026-11-08 04:56:43 +00:00
beeca26823
The riscv foundation changed the descriptor of riscv cores. We must now add "_zicsr_zifencei" to the "rv32i" designation in order to ensure we have access to CSRs and the "FENCE.I" instruction. Signed-off-by: Sean Cross <sean@xobs.io>
57 lines
1.3 KiB
Text
57 lines
1.3 KiB
Text
cpu: CPU.VexRiscv @ sysbus
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cpuType: "rv32i_zicsr_zifencei"
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PerformanceInMips: 6
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uart: UART.LiteX_UART @ {
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sysbus 0xE0003800
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}
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-> cpu@1001
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timer0: Timers.Betrusted.LiteX_Timer_32 @ {
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sysbus 0xe0001000
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}
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frequency: 100000000
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-> cpu@1000
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i2c: I2C.Betrusted.BetrustedEcI2C @ sysbus 0xE0004800
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-> cpu @ 1002
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ticktimer: Timers.Betrusted.TickTimer @ sysbus 0xe0005000
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-> cpu @ 1003
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com: SPI.Betrusted.BetrustedEcCom @ sysbus 0xe0005800
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memAddr: 0xD0000000
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memSize: 0x1000
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wifi: SPI.Betrusted.EcWifi @ sysbus 0xe0006000
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sram: Memory.MappedMemory @ {
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sysbus 0x10000000;
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sysbus 0x90000000 // shadow
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}
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size: 0x00020000
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power: Miscellaneous.Betrusted.EcPower @ sysbus 0xE0002800
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rom: Memory.MappedMemory @ {
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sysbus 0x00000000;
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sysbus 0x80000000 // shadow
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}
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size: 0x00002000
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flash_mem: Memory.MappedMemory @ {
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sysbus 0x20000000;
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sysbus 0xA0000000 // shadow
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}
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size: 0x00200000
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lm3509: Mocks.Betrusted.LM3509 @ i2c 0x36
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tusb320lai: Mocks.Betrusted.TUSB320LAI @ i2c 0x47
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bq27421: Sensors.Betrusted.BQ27421 @ i2c 0x55
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bq24157: Mocks.Betrusted.BQ24157 @ i2c 0x6a
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lsm6ds3: Mocks.Betrusted.LSM6DS3 @ i2c 0x6b
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wf200: Network.Betrusted.WF200 @ wifi
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sysbus:
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init:
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ApplySVD @ec/soc.svd
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