mirror of
https://github.com/saymrwulf/xous-core.git
synced 2026-11-13 07:48:30 +00:00
a527b3a300
RAM clearing takes a lot of time in simulation and is not necessary, hence the feature gate option.
356 lines
13 KiB
Rust
356 lines
13 KiB
Rust
use core::arch::asm;
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use crate::platform;
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// Assembly stubs for entering into the loader, and exiting it.
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// Note: inline constants are not yet stable in Rust: https://github.com/rust-lang/rust/pull/104087
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#[cfg(not(feature = "reset-debug"))]
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#[link_section = ".text.init"]
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#[export_name = "_start"]
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pub extern "C" fn _start(_kernel_args: usize, loader_sig: usize) {
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#[cfg(any(feature = "precursor", feature = "renode"))]
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let _kernel_args = _kernel_args;
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#[cfg(any(feature = "cramium-soc", feature = "cramium-fpga"))]
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let _kernel_args = platform::FLASH_BASE + platform::KERNEL_OFFSET;
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// Stub for clearing IFRAM & RAM on Cramium target. This is required
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// to clear the parity check bits, which are randomly set on boot. System will
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// eventually hang if these bits aren't cleared.
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#[cfg(all(any(feature = "cramium-soc", feature = "cramium-fpga"), not(feature = "simulation-only")))]
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unsafe {
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#[rustfmt::skip]
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asm! (
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// test if ifram is cleared
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"li t0, 0x50000000",
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"li t1, 0x50040000",
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"60:",
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"lw t2, 0(t0)",
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// if not 0, jump to clearing routine
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"bne x0, t2, 30f",
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"addi t0, t0, 4",
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// loop if we haven't checked all of ifram
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"bltu t0, t1, 60b",
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// if we got here, all of ifram was 0, continue with boot
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"j 50f",
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// clear ifram
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"30:",
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"sw x0, 0(t0)",
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"addi t0, t0, 4",
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"bltu t0, t1, 30b",
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// clear main ram
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"li t0, 0x61000000",
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"li t1, 0x61200000",
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"20:",
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"sw x0, 0(t0)",
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"addi t0, t0, 4",
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"bltu t0, t1, 20b",
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".word 0x500f",
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// reset the system
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"li t0, 0x40040080",
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"li t1, 0x55aa",
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"70:",
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"sw t1, 0(t0)",
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"j 70b", // loop forever trying to trigger the reset
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// Note that BMX access is unstable at this point in time due to the
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// high number of parity errors that were flooding the system. Thus,
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// the system has to go through a reset cycle before any further progress
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// can be made.
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// --------------------------------
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// system should be rebooting at this point, code after this
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// is unreachabale
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// --------------------------------
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// continue on boot
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"50:",
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);
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}
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unsafe {
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#[rustfmt::skip]
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asm! (
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"li t0, 0xffffffff",
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"csrw mideleg, t0",
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"csrw medeleg, t0",
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// decorate our stack area with a canary pattern
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"li t1, 0xACE0BACE",
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"mv t0, {stack_limit}",
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"mv t2, {ram_top}",
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"100:", // fillstack
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"sw t1, 0(t0)",
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"addi t0, t0, 4",
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"bltu t0, t2, 100b",
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// Place the stack pointer at the end of RAM
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"mv sp, {ram_top}",
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// subtract four from sp to make room for a DMA "gutter"
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"addi sp, sp, -4",
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// Install a machine mode trap handler
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"la t0, abort",
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"csrw mtvec, t0",
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// this forces a0/a1 to be "used" and thus not allocated for other parameters passed in
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"mv a0, {kernel_args}",
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"mv a1, {loader_sig}",
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// Start Rust
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"j rust_entry",
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kernel_args = in(reg) _kernel_args,
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loader_sig = in(reg) loader_sig,
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ram_top = in(reg) (platform::RAM_BASE + platform::RAM_SIZE),
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// On Precursor - 0x40FFE01C: currently allowed stack extent - 8k - (7 words). 7 words are for kernel backup args - see bootloader in betrusted-soc
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stack_limit = in(reg) (platform::RAM_BASE + platform::RAM_SIZE - 8192 + 7 * core::mem::size_of::<usize>()),
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options(noreturn)
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);
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}
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}
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// This is code for debugging RV32 core reset on the cramium target.
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#[cfg(feature = "reset-debug")]
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#[link_section = ".text.init"]
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#[export_name = "_start"]
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pub extern "C" fn _start(_kernel_args: usize, loader_sig: usize) {
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#[cfg(any(feature = "precursor", feature = "renode"))]
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let _kernel_args = _kernel_args;
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#[cfg(any(feature = "cramium-soc", feature = "cramium-fpga"))]
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let _kernel_args = platform::FLASH_BASE + platform::KERNEL_OFFSET;
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unsafe {
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#[rustfmt::skip]
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asm! (
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/*
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"li t0, 0x40040000",
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"li t1, 0x7f7f",
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"sw t1, 0x14(t0)",
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"sw t1, 0x18(t0)",
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"li t1, 0x3f7f",
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"sw t1, 0x1c(t0)",
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"li t1, 0x1f3f",
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"sw t1, 0x20(t0)",
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"li t1, 0x0f1f",
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"sw t1, 0x24(t0)",
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"li t1, 0xFF",
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"sw t1, 0x60(t0)",
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"sw t1, 0x64(t0)",
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"sw t1, 0x68(t0)",
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"sw t1, 0x6c(t0)",
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"li t2, 0x32",
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"sw t2, 0x2c(t0)",
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*/
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// GPIO twiddle
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/*
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"li t0, 0x5012f000",
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"li t1, 0x5550",
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"sw t1, 0x8(t0)", // AFSEL
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"li t2, 0x1803",
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"sw t2, 0x14c(t0)", // OESEL
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"sw x0, 0x134(t0)", // DAT
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"sw t2, 0x134(t0)", // DAT
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"sw x0, 0x134(t0)", // DAT
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"sw t2, 0x134(t0)", // DAT
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"sw x0, 0x134(t0)", // DAT
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"sw t2, 0x134(t0)", // DAT
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*/
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"add x1, x0, x0",
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"li x2, 0xF000",
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"20:",
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"addi x1, x1, 1",
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"bne x1, x2, 20b",
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/*
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// this, surprisingly, seems to have some effect..?
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// twiddle duart
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"li t0, 0x40042000",
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"li t1, 24",
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"sw t1, 0xc(t0)",
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"li t1, 0x1",
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"sw x0, 0x4(t0)",
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"sw t1, 0x4(t0)",
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"li t1, 0x5A",
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"sw t1, 0x0(t0)",
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*/
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// ema adjust
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/*
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"li t0, 0x40014000",
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"li t1, 0x3",
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"sw t1, 0xC(t0)",
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"sw t1, 0x10(t0)",
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"sw t1, 0x14(t0)",
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*/
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// the RAM clearing code does not have an effect
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/*
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// clear ifram
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"li t0, 0x50000000",
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"li t1, 0x50040000",
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"30:",
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"sw x0, 0(t0)",
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"addi t0, t0, 4",
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"bltu t0, t1, 30b",
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// clear main ram
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"li t0, 0x61000000",
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"li t1, 0x61200000",
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"20:",
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"sw x0, 0(t0)",
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"addi t0, t0, 4",
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"bltu t0, t1, 20b",
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".word 0x500f",
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*/
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"li t0, 0xffffffff",
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"csrw mideleg, t0",
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"csrw medeleg, t0",
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// decorate our stack area with a canary pattern
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/*
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"li t1, 0xACE0BACE",
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"mv t0, {stack_limit}",
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"mv t2, {ram_top}",
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"100:", // fillstack
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"sw t1, 0(t0)",
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"addi t0, t0, 4",
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"bltu t0, t2, 100b",
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*/
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// Place the stack pointer at the end of RAM
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// "mv sp, {ram_top}",
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"li sp, 0x61200000",
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// subtract four from sp to make room for a DMA "gutter"
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"addi sp, sp, -4",
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// Install a machine mode trap handler
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"la t0, abort",
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"csrw mtvec, t0",
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// this forces a0/a1 to be "used" and thus not allocated for other parameters passed in
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// "mv a0, {kernel_args}",
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"li a0, 0x60040000",
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"mv a1, {loader_sig}",
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// Start Rust
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"j rust_entry",
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// kernel_args = in(reg) _kernel_args,
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loader_sig = in(reg) loader_sig,
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// ram_top = in(reg) (platform::RAM_BASE + platform::RAM_SIZE),
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// On Precursor - 0x40FFE01C: currently allowed stack extent - 8k - (7 words). 7 words are for kernel backup args - see bootloader in betrusted-soc
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// stack_limit = in(reg) (platform::RAM_BASE + platform::RAM_SIZE - 8192 + 7 * core::mem::size_of::<usize>()),
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options(noreturn)
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);
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}
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}
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#[link_section = ".text.init"]
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#[export_name = "abort"]
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/// This is only used in debug mode
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pub extern "C" fn abort() -> ! {
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#[cfg(not(feature = "cramium-soc"))]
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unsafe {
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#[rustfmt::skip]
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asm!(
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"300:", // abort
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"j 300b",
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options(noreturn)
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);
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}
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#[cfg(feature = "cramium-soc")]
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unsafe {
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use utralib::generated::*;
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let uart = utra::duart::HW_DUART_BASE as *mut u32;
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while uart.add(utra::duart::SFR_SR.offset()).read_volatile() != 0 {}
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uart.add(utra::duart::SFR_TXD.offset()).write_volatile(0xa as u32);
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while uart.add(utra::duart::SFR_SR.offset()).read_volatile() != 0 {}
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uart.add(utra::duart::SFR_TXD.offset()).write_volatile(0xd as u32);
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while uart.add(utra::duart::SFR_SR.offset()).read_volatile() != 0 {}
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uart.add(utra::duart::SFR_TXD.offset()).write_volatile('0' as char as u32);
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while uart.add(utra::duart::SFR_SR.offset()).read_volatile() != 0 {}
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uart.add(utra::duart::SFR_TXD.offset()).write_volatile('x' as char as u32);
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let sc = riscv::register::scause::read();
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for &byte in sc.bits().to_be_bytes().iter() {
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let d = byte >> 4;
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let nyb = d & 0xF;
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let c = if nyb < 10 { nyb + 0x30 } else { nyb + 0x61 - 10 };
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while uart.add(utra::duart::SFR_SR.offset()).read_volatile() != 0 {}
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uart.add(utra::duart::SFR_TXD.offset()).write_volatile(c as u32);
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let d = byte & 0xF;
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let nyb = d & 0xF;
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let c = if nyb < 10 { nyb + 0x30 } else { nyb + 0x61 - 10 };
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while uart.add(utra::duart::SFR_SR.offset()).read_volatile() != 0 {}
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uart.add(utra::duart::SFR_TXD.offset()).write_volatile(c as u32);
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}
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while uart.add(utra::duart::SFR_SR.offset()).read_volatile() != 0 {}
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uart.add(utra::duart::SFR_TXD.offset()).write_volatile(0xa as u32);
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while uart.add(utra::duart::SFR_SR.offset()).read_volatile() != 0 {}
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uart.add(utra::duart::SFR_TXD.offset()).write_volatile(0xd as u32);
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loop {}
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}
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}
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#[inline(never)]
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#[export_name = "start_kernel"]
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pub extern "C" fn start_kernel(
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args: usize,
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ss: usize,
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rpt: usize,
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xpt: usize,
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satp: usize,
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entrypoint: usize,
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stack: usize,
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debug_resume: usize,
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) -> ! {
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unsafe {
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#[rustfmt::skip]
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asm! (
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// these generate redundant mv's but it ensures that the arguments are marked as used
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"mv a0, {args}",
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"mv a1, {ss}",
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"mv a2, {rpt}",
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"mv a3, {xpt}",
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// Delegate as much as we can supervisor mode
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"li t0, 0xffffffff",
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"csrw mideleg, t0",
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"csrw medeleg, t0",
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// Return to Supervisor mode (1 << 11) when we call `reti`.
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// Disable interrupts (0 << 5)
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"li t0, (1 << 11) | (0 << 5)",
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// If debug_resume is "true", also set mstatus.SUM to allow the kernel
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// to access userspace memory.
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"mv t3, {debug_resume}",
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"andi t3, t3, 1",
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"slli t3, t3, 18",
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"or t0, t0, t3",
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"csrw mstatus, t0",
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"mv a7, {debug_resume}",
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// Enable the MMU (once we issue `mret`) and flush the cache
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"csrw satp, {satp}",
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"sfence.vma",
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// Return to the address pointed to by $a4
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"csrw mepc, {entrypoint}",
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// Reposition the stack at the offset passed by $a5
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"mv sp, {stack}",
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// Issue the return, which will jump to $mepc in Supervisor mode
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"mret",
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args = in(reg) args,
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ss = in(reg) ss,
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rpt = in(reg) rpt,
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xpt = in(reg) xpt,
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satp = in(reg) satp,
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entrypoint = in(reg) entrypoint,
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stack = in(reg) stack,
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debug_resume = in(reg) debug_resume,
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options(noreturn)
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);
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}
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}
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