bunnie 069edbc255 support multi-svd file designs ... This patch set goes across all the toolchains and brings in the support for split SVD descriptions of SoCs. This is helpful for dealing with designs that have multiple "top" files for the same core IP set. For exmaple, you may have a SoC that you are developing that targets silicon, but you have a version that wraps this in additional peripherals available only in an FPGA emulator that are used for debugging. In this case, you can have one SVD file be the description of the SoC itself, and another SVD file describe just the "delta" introduced by the FPGA wrapper that emulates/controls the SoC.		2023-07-17 16:27:09 +08:00
..
bin	support multi-svd file designs	2023-07-17 16:27:09 +08:00
tags	support multi-svd file designs	2023-07-17 16:27:09 +08:00
elf.rs	elf.rs: fix alignment edge case (take 2)	2023-03-27 18:41:45 +04:00
lib.rs	tools: add sign_image.rs	2022-10-26 22:22:18 +08:00
sign_image.rs	revert #368	2023-04-21 14:16:28 +08:00
utils.rs
xous_arguments.rs	fix the assumption about all alignments being identical	2023-02-08 04:57:52 +08:00