xous-core/precursors
2023-01-03 23:25:58 +08:00
..
bbram-test1.jtg jtag script for burning the key 2021-08-04 13:57:09 +08:00
bbram-test1.nky add the test key for self-provisioning testing 2021-08-04 13:54:11 +08:00
long_8khz.wav rename as generics 2021-05-02 18:11:31 +08:00
midwinter_original.wav add audio samples for testing + credits 2021-05-02 18:04:13 +08:00
README.md move obsolete script into tools directory and update readme 2021-06-30 00:12:46 +08:00
rom.db absorb v0.9.10 soc artifacts 2022-10-09 17:53:12 +08:00
short_8khz.wav rename as generics 2021-05-02 18:11:31 +08:00
short_cd.wav rename as generics 2021-05-02 18:11:31 +08:00
soc_csr-70190e2.bin absorb 22-bit satp fix 2022-12-26 13:52:44 +08:00
soc_csr-7447604.bin commit a fixed soc image at 2022.08 2022-11-18 19:18:54 +08:00
soc_csr-a0912d6.bin move the precursor binary artifacts out of the package 2022-10-20 17:07:53 +08:00
soc_csr-c809403.bin move the precursor binary artifacts out of the package 2022-10-20 17:07:53 +08:00
soc_csr_dvt-2753c12.bin move the precursor binary artifacts out of the package 2022-10-20 17:07:53 +08:00
soc_csr_perf-c809403.bin update perf image soc to latest rev 2023-01-03 23:25:58 +08:00

Audio Samples

The .wav files included here are meant for audio testing only and are intended to be bundled into the final distribution. Developers who want to use this for testing will need to manually stage and load these samples into the correct location in the FLASH. See https://github.com/betrusted-io/xous-core/blob/master/docs/flash.md for the locations of the samples.

tools/usb_update.py can provision the "long_8khz.wav" sample that is used by the latest demo of audio playback in xous-core.

The track samples included here are from "Midwinter", by Jackalope (https://soundcloud.com/tokyojackalope)

Used with permission to redistribute as part of this repository.

SoC Prebuild

A copy of a pre-built FPGA SoC binary that matches the latest version of the current tree is also included here. It's recommended to flash this pre-build FPGA image so your kernel matches the hardware if you're only building the kernel from scratch, and not also building the FPGA hardware.