Previously, the code would only allow for reading one register at a
time. This caused that one register to be duplicated repeatedly.
As a result, readings such as Voltage were incorrect.
Signed-off-by: Sean Cross <sean@xobs.io>
This adds a working Ethernet implementation based on the WF200. It
currently gets connected to a Linux machine running a udhcpd server,
however it could also get connected to a TUN/TAP connection on Linux or
Mac.
Signed-off-by: Sean Cross <sean@xobs.io>
The COM bus is fundamentally three things: The SoC, the EC, and the glue
that binds the two together.
Now that we have the `EnsureTypeIsLoaded` trick, split the file into
three different groups.
Signed-off-by: Sean Cross <sean@xobs.io>
Emulate both the SPINOR block as well as the OSPI flash attached to it.
With this change, the PDDB can now be initialized and resets itself
properly. Additionally, data persists across virtual reboots.
Data does not persist across runs of the emulator. That will follow in
an upcoming patch.
Signed-off-by: Sean Cross <sean@xobs.io>
Previously, the HOLD signal was updated in a different clock domain from
the transmission signal. This could result in the HOLD bit being set
even if there was no data available.
Update the HOLD bit if it's present as part of the Transmit cycle.
Signed-off-by: Sean Cross <sean@xobs.io>
Connect the EC to the SoC. This allows for emulating both the EC and SoC
in tandem. Messages flow via a 16-bit bus. When data is not available,
`0xdddd` is returned.
There is a HOLD line that goes from the EC to the SoC. This is tied to
the inverse of presence of data in the EC FIFO -- when it's empty, HOLD
is `1`, and when there is data it's `0`.
Signed-off-by: Sean Cross <sean@xobs.io>
Previously, the memlcd had 22 bytes of dirty bits following a line. This
was reduced to 2 bytes, but the logic checking the dirty bytes had not
been updated.
Reduce the dirty byte count to 2 bytes.
Signed-off-by: Sean Cross <sean@xobs.io>
These registers get reset when the hardware is reset, however the engine
may still be running. Ensure it's not running when the device is reset.
Signed-off-by: Sean Cross <sean@xobs.io>
Don't consult RAM every time we want to read a register. This improves
performance at the cost of potentially having stale registers.
Signed-off-by: Sean Cross <sean@xobs.io>
The length is now correctly calculated, and the engine properly
completes.
Additionally, a bulk 512/256 implementation has been written that works
well enough, but will fall over if asked to compute a large amount of
data.
Signed-off-by: Sean Cross <sean@xobs.io>
Due to a race condition, an IRQ was always fired when the timer was
turned on.
Force a recalculation of the IRQ state when the IRQ is turned on to
avoid firing an interrupt when none should fire.
Signed-off-by: Sean Cross <sean@xobs.io>
Previously we were only checking one dirty bit, which doesn't match
what's going on with the real hardware.
Check all the bits to ensure we're accurate.
Signed-off-by: Sean Cross <sean@xobs.io>
