Commit graph

13 commits

Author SHA1 Message Date
bunnie
002a621181 change order of imports (work around rust-analyzer bug?)
I can't figure out why rust-analyzer on my system isn't work
correctly but if I change the order of imports things work better.

If this breaks things for Foundation Devices (@eupn) let me know,
I will poke at this some more and try to figure it out. In theory
it should have no impact but somehow I'm getting the atsamd target
*always* live in my vscode environment, even when it is switched
off when it isn't the last target in the list (and this overrides
all of the rust-analyzer settings for other targets).
2024-01-21 01:10:46 +08:00
bunnie
01853a500d format utralib
formatting of generated files is suppressed with a `rustfmt::skip`
directive on the `mod` import. HOWEVER, if a change is made to the
file and saved, it may still be formatted automatically until the
files are updated with codegens that put a format suppression
directive at the top
2024-01-14 23:05:01 +08:00
bunnie
2c53eb0508 add cramium targets to utralib 2023-07-17 18:24:10 +08:00
bunnie
0dd74fe7b3 remove gitrev from precursor soc type
in practice this has not been a useful indicator, and we
have stabilized the SVD format so that changes in the code don't
cause the SVD files to go incompatible anymore.

this should make maintenance a bit easier going forward, hopefully.

also merge in cramium support to harmonize the forks for easier
cross-patches in the future.
2023-03-08 03:46:03 +08:00
eupn
de296fb6c0
utralib: add SAMA5D27 svd and cargo feature 2023-03-05 16:39:23 +04:00
bunnie
08cf863ff5 update SoC artifacts for 0.9.11 build 2022-12-12 16:05:15 +08:00
bunnie
156e60d1dd fix regressions from litex 2022.08 2022-11-17 22:12:32 +08:00
bunnie
280d61db34 trial commit latest soc artifacts
updating Litex, seems to have broken things. trying to see
if a rebuild with new SVD file helps.
2022-11-17 19:37:17 +08:00
bunnie
dcbf028c5c bump soc rev
minor rev to fix a dangling git reference
2022-10-20 04:58:48 +08:00
bunnie
77e1379fc0 add SoC with new Vex core
updated codebase, hopefully pulls in fixes for cache clear
2022-10-20 04:24:00 +08:00
bunnie
74fe8c989c add dvt target
resurrecting some old hardware as an efuse testing target;
new hardware is too precious at the moment given the ridiculous
shortage of FPGAs on the market.
2022-10-18 21:47:16 +08:00
bunnie
d0dc2e2a9f add renode as a target to utralib 2022-09-27 18:09:33 +08:00
bunnie
4f7f5855ec add the generated.rs top file which routes to specific configs with feature flags 2022-09-27 16:32:40 +08:00