11 commits

Author	SHA1	Message	Date
bunnie	2c53eb0508	add cramium targets to utralib	2023-07-17 18:24:10 +08:00
bunnie	0dd74fe7b3	remove gitrev from precursor soc type ... in practice this has not been a useful indicator, and we have stabilized the SVD format so that changes in the code don't cause the SVD files to go incompatible anymore. this should make maintenance a bit easier going forward, hopefully. also merge in cramium support to harmonize the forks for easier cross-patches in the future.	2023-03-08 03:46:03 +08:00
eupn	de296fb6c0	utralib: add SAMA5D27 svd and cargo feature	2023-03-05 16:39:23 +04:00
bunnie	08cf863ff5	update SoC artifacts for 0.9.11 build	2022-12-12 16:05:15 +08:00
bunnie	156e60d1dd	fix regressions from litex 2022.08	2022-11-17 22:12:32 +08:00
bunnie	280d61db34	trial commit latest soc artifacts ... updating Litex, seems to have broken things. trying to see if a rebuild with new SVD file helps.	2022-11-17 19:37:17 +08:00
bunnie	dcbf028c5c	bump soc rev ... minor rev to fix a dangling git reference	2022-10-20 04:58:48 +08:00
bunnie	77e1379fc0	add SoC with new Vex core ... updated codebase, hopefully pulls in fixes for cache clear	2022-10-20 04:24:00 +08:00
bunnie	74fe8c989c	add dvt target ... resurrecting some old hardware as an efuse testing target; new hardware is too precious at the moment given the ridiculous shortage of FPGAs on the market.	2022-10-18 21:47:16 +08:00
bunnie	d0dc2e2a9f	add renode as a target to utralib	2022-09-27 18:09:33 +08:00
bunnie	4f7f5855ec	add the generated.rs top file which routes to specific configs with feature flags	2022-09-27 16:32:40 +08:00