Spinor is the one location where memory changes out "from underneath
the CPU" in a cacheable region. This happens when we update a block
of FLASH.
Vex-ii has a physically tagged d-cache, but the cbo.flush instruction
needs the *virtual* address to be passed (it then goes through a page
walk or TLB lookup to resolve the tag). The virtual address only
exists and can be correctly resolved to a physical address in the
process space of the owner of the region that maps to the SPINOR
FLASH. Thus, we introduce a flush routine in the lib.rs side that
calls the cbo.flush instruction on every line that has been potentially
modified by the flash write routine.
Note that cbo.flush is not yet natively supported by Rust stable,
so it's coded as a series of hex words fixed to a given register (a0)
to avoid introducing a nightly dependency. Once the cbo.flush
assembly instructions stabilize we can make the assembly read more
nicely, but functionally it should compile to exactly the same code.
This will also be the version we'll use for the daric chip once
it's available; the prior software-only version hack for MPW will
be retired soon.
Note that only AES-256 is implemented in this commit, AES-128
isn't used on the system and so is provided as a software-only
fallback path.
Note that a NACK is returned as an Ok(I2cResult::Nack) - this is
because the Err() path is still reserved for "OS failure" errors.
A Nack isn't a terminal failure, it is a recoverable fault, and
so it's handled in the Ok() path.
this is the actual handler inside the Xous service which, when
receiving the opcode, dereferences its exclusive pointer to the
IRQ bank and then returns the result to the caller.
the switch based on target is now absorbed into the new() function.
This paves the way for us to add more CSR ranges into the global
configuration object, i.e. IRQ csrs for I2C.
