diff --git a/emulation/betrusted.repl b/emulation/betrusted.repl
index fda95c6fd..0b0fde810 100644
--- a/emulation/betrusted.repl
+++ b/emulation/betrusted.repl
@@ -4,23 +4,29 @@ cpu: CPU.VexRiscv @ sysbus
privilegeArchitecture: PrivilegeArchitecture.Priv1_10
uart: UART.LiteX_UART @ {
- sysbus 0x60001000;
- sysbus 0xF0001000 // shadow
+ sysbus 0x60008000;
+ sysbus 0xF0008000 // shadow
}
-> cpu@1002
-uartkernel: UART.LiteX_UART @ {
- sysbus 0x60002000;
- sysbus 0xF0002000 // shadow
+uartconsole: UART.LiteX_UART @ {
+ sysbus 0x6000A000;
+ sysbus 0xF000A000 // shadow
}
-> cpu@1003
-uartlog: UART.LiteX_UART @ {
- sysbus 0x60004000;
- sysbus 0xF0004000 // shadow
+uartserver0: UART.LiteX_UART @ {
+ sysbus 0x6000C000;
+ sysbus 0xF000C000 // shadow
}
-> cpu@1004
+uartserver1: UART.LiteX_UART @ {
+ sysbus 0x6000E000;
+ sysbus 0xF000E000 // shadow
+ }
+ -> cpu@1005
+
timer0: Timers.LiteX_Timer_32 @ {
sysbus 0x60003000;
sysbus 0xF0003000 // shadow
@@ -48,15 +54,18 @@ sram: Memory.MappedMemory @ {
fbmem: Memory.MappedMemory @ sysbus 0xB0000000
size: 0x6000
-memlcd: Video.BetrustedLCD @ sysbus 0xF0005000
+memlcd: Video.BetrustedLCD @ sysbus 0xF0011000
kbd: Input.BetrustedKbd @ sysbus 0xF0006000
cpu_timer: Timers.LiteX_CPUTimer @ sysbus 0xf0000800
- frequency: 66000000
+ frequency: 100000000
// IRQ #100 is Machine Timer Interrupt
-> cpu@100
+ticktimer: Timers.TickTimer @ sysbus 0xf0016000
+ periodInMs: 1
+
//flash: SPI.Micron_MT25Q @ spi
// underlyingMemory: flash_mem
diff --git a/emulation/boot.resc b/emulation/boot.resc
index 8a0bea135..da37e7408 100644
--- a/emulation/boot.resc
+++ b/emulation/boot.resc
@@ -12,14 +12,16 @@ mach create
i @peripherals/LiteX_Timer_32.cs
i @peripherals/memlcd.cs
i @peripherals/keyboard.cs
+i @peripherals/ticktimer.cs
# Load the Betrusted Renode Platform file
machine LoadPlatformDescription @betrusted.repl
machine StartGdbServer 3333 true
showAnalyzer uart
-showAnalyzer uartlog
-showAnalyzer uartkernel
+showAnalyzer uartconsole
+showAnalyzer uartserver0
+showAnalyzer uartserver1
showAnalyzer memlcd
logLevel -1 kbd
diff --git a/emulation/peripherals/ticktimer.cs b/emulation/peripherals/ticktimer.cs
new file mode 100644
index 000000000..6040ddd30
--- /dev/null
+++ b/emulation/peripherals/ticktimer.cs
@@ -0,0 +1,83 @@
+//
+// Copyright (c) 2010-2019 Antmicro
+//
+// This file is licensed under the MIT License.
+// Full license text is available in 'licenses/MIT.txt'.
+//
+using System;
+using Antmicro.Renode.Core;
+using Antmicro.Renode.Core.Structure.Registers;
+using Antmicro.Renode.Utilities;
+using Antmicro.Renode.Logging;
+using Antmicro.Renode.Time;
+using Antmicro.Renode.Peripherals.Bus;
+using System.Threading;
+
+namespace Antmicro.Renode.Peripherals.Timers
+{
+ // this is a model of LiteX timer in the Betrusted configuration:
+ // * width: 32 bits
+ // * csr data width: 32 bit
+ [AllowedTranslations(AllowedTranslation.ByteToDoubleWord)]
+ public class TickTimer : BasicDoubleWordPeripheral, IKnownSize
+ {
+ public TickTimer(Machine machine, ulong periodInMs) : base(machine)
+ {
+ machine.ClockSource.AddClockEntry(new ClockEntry(periodInMs, ClockEntry.FrequencyToRatio(this, 1000), OnTick, this, "TickTimer"));
+ DefineRegisters();
+ }
+
+ public override void Reset()
+ {
+ base.Reset();
+ tickValue = 0;
+ paused = true;
+ }
+
+ private void OnTick()
+ {
+ if (!paused) {
+ Interlocked.Increment(ref tickValue);
+ }
+ }
+
+ public long Size { get { return 0x20; }}
+
+ private void DefineRegisters()
+ {
+ Registers.Control.Define32(this)
+ .WithValueField(0, 32, name: "CONTROL", writeCallback: (_, val) =>
+ {
+ if ((val & 1) != 0) {
+ tickValue = 0;
+ }
+ paused = (val & 2) != 0;
+ });
+ ;
+
+ Registers.Time1.Define32(this)
+ .WithValueField(0, 32, FieldMode.Read, name: "Time1", valueProviderCallback: _ =>
+ {
+ return (uint) (tickValue >> 32);
+ })
+ ;
+
+ Registers.Time0.Define32(this)
+ .WithValueField(0, 32, FieldMode.Read, name: "Time0", valueProviderCallback: _ =>
+ {
+ return (uint) (tickValue >> 0);
+ })
+ ;
+ }
+
+ bool paused;
+ long tickValue;
+
+ private enum Registers
+ {
+ Control = 0x00,
+ Time1 = 0x04,
+ Time0 = 0x08,
+ }
+ }
+}
diff --git a/emulation/renode.svd b/emulation/renode.svd
index 84655cb20..05752ca97 100644
--- a/emulation/renode.svd
+++ b/emulation/renode.svd
@@ -102,172 +102,9 @@ to the Wishbone/CSR bus are working correctly. The initial reset value of
registers
-
- UART_PHY
- 0xF0003000
- UART_PHY
-
-
- TUNING_WORD
- 0x0000
- 0x4b7f5a
- 32
- read-write
-
-
- tuning_word
- 31
- [31:0]
- 0
-
-
-
-
-
- 0
- 0x4
- registers
-
-
-
- UART
- 0xF0004000
- UART
-
-
- RXTX
- 0x0000
- 0x00
- 32
- read-write
-
-
- rxtx
- 7
- [7:0]
- 0
-
-
-
-
- TXFULL
- 0x0004
- 0x00
- 32
- read-only
-
-
- txfull
- 0
- [0:0]
- 0
-
-
-
-
- RXEMPTY
- 0x0008
- 0x00
- 32
- read-only
-
-
- rxempty
- 0
- [0:0]
- 0
-
-
-
-
- EV_STATUS
- 0x000c
- 0x00
- 32
- read-write
-
-
- status
- 1
- [1:0]
- 0
-
-
-
-
- EV_PENDING
- 0x0010
- 0x00
- 32
- read-write
-
-
- pending
- 1
- [1:0]
- 0
-
-
-
-
- EV_ENABLE
- 0x0014
- 0x00
- 32
- read-write
-
-
- enable
- 1
- [1:0]
- 0
-
-
-
-
- TXEMPTY
- 0x0018
- 0x00
- 32
- read-only
-
-
- txempty
- 0
- [0:0]
- 0
-
-
-
-
- RXFULL
- 0x001c
- 0x00
- 32
- read-only
-
-
- rxfull
- 0
- [0:0]
- 0
-
-
-
-
-
- 0
- 0x20
- registers
-
-
- uart
- 0
-
-
TIMER0
- 0xF0005000
+ 0xF0003000
TIMER0
@@ -407,12 +244,12 @@ the current countdown value to ``value`` register.]]>
timer0
- 1
+ 0
REBOOT
- 0xF0006000
+ 0xF0004000
REBOOT
@@ -454,7 +291,7 @@ the current countdown value to ``value`` register.]]>
CRG
- 0xF0007000
+ 0xF0005000
CRG
@@ -585,8 +422,819 @@ the current countdown value to ``value`` register.]]>
- INFO
+ GPIO
+ 0xF0006000
+ GPIO
+
+
+ OUTPUT
+
+ 0x0000
+ 0x00
+ 32
+ read-write
+
+
+ output
+ 5
+ [5:0]
+ 0
+
+
+
+
+ INPUT
+
+ 0x0004
+ 0x00
+ 32
+ read-only
+
+
+ input
+ 5
+ [5:0]
+ 0
+
+
+
+
+ DRIVE
+
+ 0x0008
+ 0x00
+ 32
+ read-write
+
+
+ drive
+ 5
+ [5:0]
+ 0
+
+
+
+
+ INTENA
+
+ 0x000c
+ 0x00
+ 32
+ read-only
+
+
+ intena
+ 5
+ [5:0]
+ 0
+
+
+
+
+ INTPOL
+
+ 0x0010
+ 0x00
+ 32
+ read-only
+
+
+ intpol
+ 5
+ [5:0]
+ 0
+
+
+
+
+ UARTSEL
+
+ 0x0014
+ 0x00
+ 32
+ read-write
+
+
+ uartsel
+ 1
+ [1:0]
+ 0
+
+
+
+
+ EV_STATUS
+ 0x0018
+ 0x00
+ 32
+ read-write
+
+
+ status
+ 5
+ [5:0]
+ 0
+
+
+
+
+ EV_PENDING
+ 0x001c
+ 0x00
+ 32
+ read-write
+
+
+ pending
+ 5
+ [5:0]
+ 0
+
+
+
+
+ EV_ENABLE
+ 0x0020
+ 0x00
+ 32
+ read-write
+
+
+ enable
+ 5
+ [5:0]
+ 0
+
+
+
+
+
+ 0
+ 0x24
+ registers
+
+
+ gpio
+ 1
+
+
+
+ UART_PHY
+ 0xF0007000
+ UART_PHY
+
+
+ TUNING_WORD
+ 0x0000
+ 0x4b7f5a
+ 32
+ read-write
+
+
+ tuning_word
+ 31
+ [31:0]
+ 0
+
+
+
+
+
+ 0
+ 0x4
+ registers
+
+
+
+ UART
0xF0008000
+ UART
+
+
+ RXTX
+ 0x0000
+ 0x00
+ 32
+ read-write
+
+
+ rxtx
+ 7
+ [7:0]
+ 0
+
+
+
+
+ TXFULL
+ 0x0004
+ 0x00
+ 32
+ read-only
+
+
+ txfull
+ 0
+ [0:0]
+ 0
+
+
+
+
+ RXEMPTY
+ 0x0008
+ 0x00
+ 32
+ read-only
+
+
+ rxempty
+ 0
+ [0:0]
+ 0
+
+
+
+
+ EV_STATUS
+ 0x000c
+ 0x00
+ 32
+ read-write
+
+
+ status
+ 1
+ [1:0]
+ 0
+
+
+
+
+ EV_PENDING
+ 0x0010
+ 0x00
+ 32
+ read-write
+
+
+ pending
+ 1
+ [1:0]
+ 0
+
+
+
+
+ EV_ENABLE
+ 0x0014
+ 0x00
+ 32
+ read-write
+
+
+ enable
+ 1
+ [1:0]
+ 0
+
+
+
+
+ TXEMPTY
+ 0x0018
+ 0x00
+ 32
+ read-only
+
+
+ txempty
+ 0
+ [0:0]
+ 0
+
+
+
+
+ RXFULL
+ 0x001c
+ 0x00
+ 32
+ read-only
+
+
+ rxfull
+ 0
+ [0:0]
+ 0
+
+
+
+
+
+ 0
+ 0x20
+ registers
+
+
+ uart
+ 2
+
+
+
+ CONSOLE_PHY
+ 0xF0009000
+ CONSOLE_PHY
+
+
+ TUNING_WORD
+ 0x0000
+ 0x4b7f5a
+ 32
+ read-write
+
+
+ tuning_word
+ 31
+ [31:0]
+ 0
+
+
+
+
+
+ 0
+ 0x4
+ registers
+
+
+
+ CONSOLE
+ 0xF000A000
+ CONSOLE
+
+
+ RXTX
+ 0x0000
+ 0x00
+ 32
+ read-write
+
+
+ rxtx
+ 7
+ [7:0]
+ 0
+
+
+
+
+ TXFULL
+ 0x0004
+ 0x00
+ 32
+ read-only
+
+
+ txfull
+ 0
+ [0:0]
+ 0
+
+
+
+
+ RXEMPTY
+ 0x0008
+ 0x00
+ 32
+ read-only
+
+
+ rxempty
+ 0
+ [0:0]
+ 0
+
+
+
+
+ EV_STATUS
+ 0x000c
+ 0x00
+ 32
+ read-write
+
+
+ status
+ 1
+ [1:0]
+ 0
+
+
+
+
+ EV_PENDING
+ 0x0010
+ 0x00
+ 32
+ read-write
+
+
+ pending
+ 1
+ [1:0]
+ 0
+
+
+
+
+ EV_ENABLE
+ 0x0014
+ 0x00
+ 32
+ read-write
+
+
+ enable
+ 1
+ [1:0]
+ 0
+
+
+
+
+ TXEMPTY
+ 0x0018
+ 0x00
+ 32
+ read-only
+
+
+ txempty
+ 0
+ [0:0]
+ 0
+
+
+
+
+ RXFULL
+ 0x001c
+ 0x00
+ 32
+ read-only
+
+
+ rxfull
+ 0
+ [0:0]
+ 0
+
+
+
+
+
+ 0
+ 0x20
+ registers
+
+
+ console
+ 3
+
+
+
+ SERVER0_PHY
+ 0xF000B000
+ SERVER0_PHY
+
+
+ TUNING_WORD
+ 0x0000
+ 0x4b7f5a
+ 32
+ read-write
+
+
+ tuning_word
+ 31
+ [31:0]
+ 0
+
+
+
+
+
+ 0
+ 0x4
+ registers
+
+
+
+ SERVER0
+ 0xF000C000
+ SERVER0
+
+
+ RXTX
+ 0x0000
+ 0x00
+ 32
+ read-write
+
+
+ rxtx
+ 7
+ [7:0]
+ 0
+
+
+
+
+ TXFULL
+ 0x0004
+ 0x00
+ 32
+ read-only
+
+
+ txfull
+ 0
+ [0:0]
+ 0
+
+
+
+
+ RXEMPTY
+ 0x0008
+ 0x00
+ 32
+ read-only
+
+
+ rxempty
+ 0
+ [0:0]
+ 0
+
+
+
+
+ EV_STATUS
+ 0x000c
+ 0x00
+ 32
+ read-write
+
+
+ status
+ 1
+ [1:0]
+ 0
+
+
+
+
+ EV_PENDING
+ 0x0010
+ 0x00
+ 32
+ read-write
+
+
+ pending
+ 1
+ [1:0]
+ 0
+
+
+
+
+ EV_ENABLE
+ 0x0014
+ 0x00
+ 32
+ read-write
+
+
+ enable
+ 1
+ [1:0]
+ 0
+
+
+
+
+ TXEMPTY
+ 0x0018
+ 0x00
+ 32
+ read-only
+
+
+ txempty
+ 0
+ [0:0]
+ 0
+
+
+
+
+ RXFULL
+ 0x001c
+ 0x00
+ 32
+ read-only
+
+
+ rxfull
+ 0
+ [0:0]
+ 0
+
+
+
+
+
+ 0
+ 0x20
+ registers
+
+
+ server0
+ 4
+
+
+
+ SERVER1_PHY
+ 0xF000D000
+ SERVER1_PHY
+
+
+ TUNING_WORD
+ 0x0000
+ 0x4b7f5a
+ 32
+ read-write
+
+
+ tuning_word
+ 31
+ [31:0]
+ 0
+
+
+
+
+
+ 0
+ 0x4
+ registers
+
+
+
+ SERVER1
+ 0xF000E000
+ SERVER1
+
+
+ RXTX
+ 0x0000
+ 0x00
+ 32
+ read-write
+
+
+ rxtx
+ 7
+ [7:0]
+ 0
+
+
+
+
+ TXFULL
+ 0x0004
+ 0x00
+ 32
+ read-only
+
+
+ txfull
+ 0
+ [0:0]
+ 0
+
+
+
+
+ RXEMPTY
+ 0x0008
+ 0x00
+ 32
+ read-only
+
+
+ rxempty
+ 0
+ [0:0]
+ 0
+
+
+
+
+ EV_STATUS
+ 0x000c
+ 0x00
+ 32
+ read-write
+
+
+ status
+ 1
+ [1:0]
+ 0
+
+
+
+
+ EV_PENDING
+ 0x0010
+ 0x00
+ 32
+ read-write
+
+
+ pending
+ 1
+ [1:0]
+ 0
+
+
+
+
+ EV_ENABLE
+ 0x0014
+ 0x00
+ 32
+ read-write
+
+
+ enable
+ 1
+ [1:0]
+ 0
+
+
+
+
+ TXEMPTY
+ 0x0018
+ 0x00
+ 32
+ read-only
+
+
+ txempty
+ 0
+ [0:0]
+ 0
+
+
+
+
+ RXFULL
+ 0x001c
+ 0x00
+ 32
+ read-only
+
+
+ rxfull
+ 0
+ [0:0]
+ 0
+
+
+
+
+
+ 0
+ 0x20
+ registers
+
+
+ server1
+ 5
+
+
+
+ INFO
+ 0xF000F000
INFO
@@ -1007,7 +1655,7 @@ VCCBRAM (V) = ``Value`` x 3 / 4096.]]>
SRAM_EXT
- 0xF0009000
+ 0xF0010000
SRAM_EXT
@@ -1051,7 +1699,7 @@ VCCBRAM (V) = ``Value`` x 3 / 4096.]]>
MEMLCD
- 0xF000A000
+ 0xF0011000
MEMLCD
@@ -1164,7 +1812,7 @@ VCCBRAM (V) = ``Value`` x 3 / 4096.]]>
COM
- 0xF000B000
+ 0xF0012000
COM
@@ -1285,7 +1933,7 @@ VCCBRAM (V) = ``Value`` x 3 / 4096.]]>
I2C
- 0xF000C000
+ 0xF0013000
I2C
@@ -1533,12 +2181,12 @@ upon the completion of one byte of data transfer.]]>
i2c
- 2
+ 6
BTEVENTS
- 0xF000D000
+ 0xF0014000
BTEVENTS
@@ -1594,12 +2242,12 @@ upon the completion of one byte of data transfer.]]>
btevents
- 3
+ 7
MESSIBLE
- 0xF000E000
+ 0xF0015000
MESSIBLE
@@ -1668,7 +2316,7 @@ register advances the read pointer automatically.]]>
TICKTIMER
- 0xF000F000
+ 0xF0016000
TICKTIMER
@@ -1735,7 +2383,7 @@ register advances the read pointer automatically.]]>
POWER
- 0xF0010000
+ 0xF0017000
POWER
@@ -1894,7 +2542,7 @@ reset fashion]]>
SPINOR
- 0xF0011000
+ 0xF0018000
SPINOR
@@ -2105,7 +2753,7 @@ checked]]>
KEYBOARD
- 0xF0012000
+ 0xF0019000
KEYBOARD
@@ -2322,161 +2970,19 @@ again until the interrupt is serviced.]]>
keyboard
- 4
-
-
-
- GPIO
- 0xF0013000
- GPIO
-
-
- OUTPUT
-
- 0x0000
- 0x00
- 32
- read-write
-
-
- output
- 5
- [5:0]
- 0
-
-
-
-
- INPUT
-
- 0x0004
- 0x00
- 32
- read-only
-
-
- input
- 5
- [5:0]
- 0
-
-
-
-
- DRIVE
-
- 0x0008
- 0x00
- 32
- read-write
-
-
- drive
- 5
- [5:0]
- 0
-
-
-
-
- INTENA
-
- 0x000c
- 0x00
- 32
- read-only
-
-
- intena
- 5
- [5:0]
- 0
-
-
-
-
- INTPOL
-
- 0x0010
- 0x00
- 32
- read-only
-
-
- intpol
- 5
- [5:0]
- 0
-
-
-
-
- EV_STATUS
- 0x0014
- 0x00
- 32
- read-write
-
-
- status
- 5
- [5:0]
- 0
-
-
-
-
- EV_PENDING
- 0x0018
- 0x00
- 32
- read-write
-
-
- pending
- 5
- [5:0]
- 0
-
-
-
-
- EV_ENABLE
- 0x001c
- 0x00
- 32
- read-write
-
-
- enable
- 5
- [5:0]
- 0
-
-
-
-
-
- 0
- 0x20
- registers
-
-
- gpio
- 5
+ 8
SEED
- 0xF0014000
+ 0xF001A000
SEED
SEED1
0x0000
- 0x64f83336
+ 0xd261d6d
32
read-only
@@ -2492,7 +2998,7 @@ interrupts.]]>
SEED0
0x0004
- 0x60e6ef3
+ 0x541ad152
32
read-only
@@ -2513,7 +3019,7 @@ interrupts.]]>
ROMTEST
- 0xF0015000
+ 0xF001B000
ROMTEST
@@ -2557,7 +3063,7 @@ interrupts.]]>
AUDIO
- 0xF0016000
+ 0xF001C000
AUDIO
@@ -2864,12 +3370,12 @@ I2S_FORMAT.I2S_STANDARD is I2S standard]]>
audio
- 6
+ 9
TRNG_OSC
- 0xF0017000
+ 0xF001D000
TRNG_OSC
@@ -2958,7 +3464,7 @@ reading the `rand` register]]>
AES
- 0xF0018000
+ 0xF001E000
AES
@@ -3444,7 +3950,7 @@ automatically on data and IV ready]]>
SHA2
- 0xF0019000
+ 0xF001F000
SHA2
@@ -3934,12 +4440,12 @@ automatically on data and IV ready]]>
sha2
- 7
+ 10
SHA512
- 0xF001A000
+ 0xF0020000
SHA512
@@ -4405,12 +4911,12 @@ in bits]]>
sha512
- 8
+ 11
ENGINE
- 0xF001B000
+ 0xF0021000
ENGINE
@@ -4616,12 +5122,12 @@ exactly reflects the binary layout of an Engine instruction.]]>
engine
- 9
+ 12
JTAG
- 0xF001C000
+ 0xF0022000
JTAG
@@ -4739,4 +5245,4 @@ exactly reflects the binary layout of an Engine instruction.]]>
-
\ No newline at end of file
+