mirror of
https://github.com/saymrwulf/xous-core.git
synced 2026-11-12 07:44:18 +00:00
bug fixes to frame buffer driver for cramium target
now works, and works pretty well.
This commit is contained in:
bunnie
parent
37d35b8e27
commit
f06ceea5e1
1 changed files with 46 additions and 38 deletions
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@ -63,6 +63,8 @@
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//! is a fairly long setup/hold time requirement on it and there does not seem
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//! to be a provision in the UDMA block to put guardbands around the CS timing.
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use core::mem::size_of;
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use cram_hal_service::IoxHal;
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use cramium_hal::udma::PeriphId;
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use cramium_hal::{iox, udma};
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@ -75,7 +77,10 @@ pub const FB_WIDTH_WORDS: usize = 11;
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pub const FB_WIDTH_PIXELS: usize = WIDTH as usize;
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pub const FB_LINES: usize = LINES as usize;
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pub const FB_SIZE: usize = FB_WIDTH_WORDS * FB_LINES; // 44 bytes by 536 lines
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const CONFIG_CLOCK_FREQUENCY: u32 = 100_000_000;
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// TODO: need to confirm actual clock sent to UDMA block, but empirically, this is what I see
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// on the FPGA emulator
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const CONFIG_CLOCK_FREQUENCY: u32 = 50_000_000;
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const SPI_CS_PIN: u8 = 10;
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const SPI_CLK_PIN: u8 = 7;
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@ -117,8 +122,6 @@ impl XousDisplay {
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}
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}
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// TODO:
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// - then convert the line below to create a Spim, instead of an IframRange...
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let udma_global = cram_hal_service::UdmaGlobal::new();
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// using bank SPIM_B[1]
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udma_global.udma_clock_config(PeriphId::Spim1, true);
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@ -129,13 +132,15 @@ impl XousDisplay {
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cramium_hal::udma::Spim::new(
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udma::SpimChannel::Channel1,
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2_000_000,
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100_000_000,
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CONFIG_CLOCK_FREQUENCY,
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udma::SpimClkPol::LeadingEdgeRise,
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udma::SpimClkPha::CaptureOnTrailing,
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udma::SpimClkPha::CaptureOnLeading,
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udma::SpimCs::Cs0,
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3,
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2,
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None,
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// one extra line for handling the addressing setup
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FB_SIZE + FB_WIDTH_WORDS * 4,
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(FB_LINES + 1) * FB_WIDTH_WORDS * size_of::<u32>(),
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0,
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)
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.expect("Couldn't allocate SPI channel for LCD")
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@ -165,12 +170,14 @@ impl XousDisplay {
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Some(iox::IoxEnable::Enable),
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Some(iox::IoxDriveStrength::Drive2mA),
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);
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// SPIM_SCSN0_B[1] - as GPIO
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// SPIM_SCSN0_B[1]
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// chip select toggle by UDMA has ~6 cycles setup and 1 cycles hold time, which
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// meets the requirements for the display.
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iox.setup_io_pin(
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SPI_PORT,
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SPI_CS_PIN,
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Some(iox::IoxDir::Output),
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Some(iox::IoxFunction::Gpio),
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Some(iox::IoxFunction::AF2),
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None,
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Some(iox::IoxEnable::Enable),
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Some(iox::IoxEnable::Enable),
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@ -197,7 +204,7 @@ impl XousDisplay {
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/// The addresses of these structures are passed as `u32` and unsafely cast back
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/// into pointers on the user's side. We do this because the panic handler is special:
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/// it grabs ahold of the low-level hardware, yanking control from the higher level
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/// control functons, without having to map its own separate pages.
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/// control functions, without having to map its own separate pages.
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///
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/// Of course, "anyone" with a copy of this data can clobber existing graphics operations. Thus,
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/// any access to these registers have to be protected with a mutex of some form. In the case of
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@ -269,7 +276,7 @@ impl XousDisplay {
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// this code is safe because u32 is representable on the system
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let fb = unsafe { self.fb.as_slice_mut::<u32>() };
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// copy to the soft frame buffer
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fb.copy_from_slice(bmp);
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fb[..bmp.len()].copy_from_slice(bmp);
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// now copy for DMA
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for line_no in 0..FB_LINES {
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self.copy_line_to_dma(line_no);
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@ -288,51 +295,52 @@ impl XousDisplay {
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/// Copies a display line to the DMA buffer, while setting up all the bits for
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/// the DMA operation. Manages the DMA line pointer as well.
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fn copy_line_to_dma(&mut self, src_line: usize) {
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// safety: this is safe because the underlying data types (u32) are representable on the system
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unsafe {
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let hwfb = self.spim.tx_buf_mut();
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let fb = self.fb.as_slice::<u32>();
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// set the mode and address
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// the very first line is unused, except for the mode & address info
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// this is done just to keep the math easy for computing strides & alignments
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hwfb[(self.next_free_line + 1) * FB_WIDTH_WORDS - 1] =
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(hwfb[(self.next_free_line + 1) * FB_WIDTH_WORDS - 1] & 0x0000_FFFFF)
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| ((src_line as u32) << 6)
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| 0b001;
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// now copy the data
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hwfb[(self.next_free_line + 1) * FB_WIDTH_WORDS..(self.next_free_line + 2) * FB_WIDTH_WORDS]
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.copy_from_slice(&fb[src_line * FB_WIDTH_WORDS..(src_line + 1) * FB_WIDTH_WORDS]);
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if self.devboot && src_line == 7 {
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for w in hwfb
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[(self.next_free_line + 1) * FB_WIDTH_WORDS..(self.next_free_line + 2) * FB_WIDTH_WORDS]
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.iter_mut()
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{
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*w = *w & 0xCCCC_CCCC; // hash over the status line
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}
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let hwfb = self.spim.tx_buf_mut();
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// safety: this is safe because `u32` has no invalid values
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let fb = unsafe { self.fb.as_slice::<u32>() };
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// set the mode and address
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// the very first line is unused, except for the mode & address info
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// this is done just to keep the math easy for computing strides & alignments
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hwfb[(self.next_free_line + 1) * FB_WIDTH_WORDS - 1] =
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(hwfb[(self.next_free_line + 1) * FB_WIDTH_WORDS - 1] & 0x0000_FFFF)
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| (((src_line as u32) << 6) | 0b001) << 16;
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// now copy the data
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hwfb[(self.next_free_line + 1) * FB_WIDTH_WORDS..(self.next_free_line + 2) * FB_WIDTH_WORDS]
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.copy_from_slice(&fb[src_line * FB_WIDTH_WORDS..(src_line + 1) * FB_WIDTH_WORDS]);
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if self.devboot && src_line == 7 {
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for w in hwfb
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[(self.next_free_line + 1) * FB_WIDTH_WORDS..(self.next_free_line + 2) * FB_WIDTH_WORDS]
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.iter_mut()
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{
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*w = *w & 0xCCCC_CCCC; // hash over the status line
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}
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}
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if self.next_free_line < LINES as usize {
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self.next_free_line += 1;
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} else {
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log::warn!(
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"Line overflow in DMA detected. Suspect missing `update_dirty` call. Further lines will overwrite the last line."
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);
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}
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}
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fn update_dirty(&mut self) {
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if self.next_free_line != 0 {
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// manual toggle of CS pins is necessary in part to meet setup/hold time of the LCD
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self.iox.set_gpio_pin_value(SPI_PORT, SPI_CS_PIN, iox::IoxValue::High);
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// safety: this function is safe to call because:
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// - `is_virtual` is `false` => data should be a physical buffer that is pre-populated with the
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// transmit data this is done by `copy_line_to_dma()`
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// - the `data` argument is a physical buffer slice, which is only used as a base/bounds
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// argument
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unsafe {
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self.spim.tx_data_async_from_parts::<u32>(
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FB_WIDTH_WORDS - 1,
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(self.next_free_line + 1) * FB_WIDTH_WORDS,
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false,
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self.spim.tx_data_async_from_parts::<u16>(
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FB_WIDTH_WORDS * 2 - 1,
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// +1 for the trailing dummy bits
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self.next_free_line * FB_WIDTH_WORDS * 2 + 1,
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true,
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false,
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);
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}
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self.iox.set_gpio_pin_value(SPI_PORT, SPI_CS_PIN, iox::IoxValue::Low);
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self.next_free_line = 0;
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}
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}
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