mirror of
https://github.com/saymrwulf/xous-core.git
synced 2026-11-15 08:30:02 +00:00
update latest SVDs to RTL
This commit is contained in:
bunnie
parent
f49cab6ca7
commit
f04d7bebe7
4 changed files with 772 additions and 130 deletions
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@ -3,7 +3,7 @@
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|||
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
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<vendor>litex</vendor>
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<name>SOC</name>
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<description><![CDATA[Litex SoC 2023-08-20 16:58:47]]></description>
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<description><![CDATA[Litex SoC 2023-09-15 20:42:25]]></description>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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@ -5629,6 +5629,21 @@ bit position to clear the flag]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>SFR_OPTLTX</name>
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<addressOffset>0x0018</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>sfr_optltx</name>
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<msb>3</msb>
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<bitRange>[3:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[sfr_optltx read/write control register]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>SFR_SEGPTR_PTRID_IV</name>
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<addressOffset>0x0030</addressOffset>
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@ -5782,6 +5797,22 @@ bit position to clear the flag]]></description>
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<bitRange>[3:3]</bitRange>
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<lsb>3</lsb>
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<description><![CDATA[chnli_done flag register. `1` means event happened, write back `1` in respective
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bit position to clear the flag]]></description>
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</field>
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<field>
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<name>chkdone</name>
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<msb>4</msb>
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<bitRange>[4:4]</bitRange>
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<lsb>4</lsb>
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<description><![CDATA[chkdone flag register. `1` means event happened, write back `1` in respective
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bit position to clear the flag]]></description>
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</field>
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<field>
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<name>chkpass</name>
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<msb>5</msb>
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<bitRange>[5:5]</bitRange>
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<lsb>5</lsb>
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<description><![CDATA[chkpass flag register. `1` means event happened, write back `1` in respective
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bit position to clear the flag]]></description>
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</field>
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</fields>
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@ -5845,6 +5876,21 @@ bit position to clear the flag]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>SFR_BLKT0</name>
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<addressOffset>0x001c</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>sfr_blkt0</name>
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<msb>7</msb>
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<bitRange>[7:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[sfr_blkt0 read/write control register]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>SFR_SEGPTR_SEGID_LKEY</name>
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<addressOffset>0x0020</addressOffset>
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@ -5921,13 +5967,13 @@ bit position to clear the flag]]></description>
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</fields>
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</register>
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<register>
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<name>SFR_SEGPTR_SEGID_SOB</name>
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<addressOffset>0x0038</addressOffset>
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<name>SFR_SEGPTR_SEGID_HOUT2</name>
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<addressOffset>0x003c</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>SEGID_SOB</name>
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<name>SEGID_HOUT2</name>
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<msb>11</msb>
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<bitRange>[11:0]</bitRange>
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<lsb>0</lsb>
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@ -5938,7 +5984,7 @@ bit position to clear the flag]]></description>
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</registers>
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<addressBlock>
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<offset>0</offset>
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<size>0x3c</size>
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<size>0x40</size>
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<usage>registers</usage>
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</addressBlock>
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</peripheral>
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@ -5954,11 +6000,18 @@ bit position to clear the flag]]></description>
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<size>32</size>
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<fields>
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<field>
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<name>sfr_crfunc</name>
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<name>cr_func</name>
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<msb>7</msb>
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<bitRange>[7:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[sfr_crfunc read/write control register]]></description>
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<description><![CDATA[cr_func read/write control register]]></description>
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</field>
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<field>
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<name>cr_pcoreir</name>
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<msb>15</msb>
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<bitRange>[15:8]</bitRange>
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<lsb>8</lsb>
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<description><![CDATA[cr_pcoreir read/write control register]]></description>
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</field>
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</fields>
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</register>
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@ -6077,6 +6130,36 @@ bit position to clear the flag]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>SFR_OPTRW</name>
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<addressOffset>0x0018</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>sfr_optrw</name>
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<msb>9</msb>
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<bitRange>[9:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[sfr_optrw read/write control register]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>SFR_OPTLTX</name>
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<addressOffset>0x001c</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>sfr_optltx</name>
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<msb>4</msb>
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<bitRange>[4:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[sfr_optltx read/write control register]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>SFR_OPTMASK</name>
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<addressOffset>0x0020</addressOffset>
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@ -6569,17 +6652,18 @@ position to clear the flag]]></description>
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</fields>
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</register>
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<register>
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<name>SFR_TICKCYC</name>
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<name>SFR_FRACERR</name>
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<addressOffset>0x0020</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>sfr_tickcyc</name>
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<name>fr_acerr</name>
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<msb>7</msb>
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<bitRange>[7:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[sfr_tickcyc read/write control register]]></description>
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<description><![CDATA[fr_acerr flag register. `1` means event happened, write back `1` in respective
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bit position to clear the flag]]></description>
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</field>
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</fields>
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</register>
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@ -6718,10 +6802,25 @@ position to clear the flag]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>SFR_TS</name>
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<addressOffset>0x00fc</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>cr_ts</name>
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<msb>15</msb>
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<bitRange>[15:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[cr_ts read/write control register]]></description>
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</field>
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</fields>
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</register>
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</registers>
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<addressBlock>
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<offset>0</offset>
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<size>0x58</size>
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<size>0x100</size>
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<usage>registers</usage>
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</addressBlock>
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</peripheral>
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@ -6746,17 +6845,17 @@ position to clear the flag]]></description>
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</fields>
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</register>
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<register>
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<name>SFR_AR_STOP</name>
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<name>SFR_CRANA</name>
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<addressOffset>0x0004</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>sfr_ar_stop</name>
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<msb>31</msb>
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<bitRange>[31:0]</bitRange>
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<name>sfr_crana</name>
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<msb>15</msb>
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<bitRange>[15:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[sfr_ar_stop performs action on write of value: 0xa5]]></description>
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<description><![CDATA[sfr_crana read/write control register]]></description>
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</field>
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</fields>
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</register>
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@ -6805,10 +6904,71 @@ position to clear the flag]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>SFR_AR_GEN</name>
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<addressOffset>0x0014</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>sfr_ar_gen</name>
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<msb>31</msb>
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<bitRange>[31:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[sfr_ar_gen performs action on write of value: 0x55]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>SFR_FR</name>
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<addressOffset>0x0018</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>sfr_fr</name>
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<msb>1</msb>
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<bitRange>[1:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[sfr_fr flag register. `1` means event happened, write back `1` in respective bit
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position to clear the flag]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>SFR_CHAIN_RNGCHAINEN0</name>
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<addressOffset>0x0040</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>rngchainen0</name>
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<msb>31</msb>
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<bitRange>[31:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[sfr_chain read/write control register]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>SFR_CHAIN_RNGCHAINEN1</name>
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<addressOffset>0x0044</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>rngchainen1</name>
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<msb>31</msb>
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<bitRange>[31:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[sfr_chain read/write control register]]></description>
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</field>
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</fields>
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</register>
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</registers>
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<addressBlock>
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<offset>0</offset>
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<size>0x14</size>
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<size>0x48</size>
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<usage>registers</usage>
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</addressBlock>
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</peripheral>
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@ -7316,13 +7476,13 @@ position to clear the flag]]></description>
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</fields>
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</register>
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<register>
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<name>SFR_CGUFD_CFGFDCR0</name>
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<name>SFR_CGUFD_CFGFDCR_0_4_0</name>
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<addressOffset>0x0014</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>cfgfdcr0</name>
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<name>cfgfdcr_0_4_0</name>
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<msb>15</msb>
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<bitRange>[15:0]</bitRange>
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<lsb>0</lsb>
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@ -7331,13 +7491,13 @@ position to clear the flag]]></description>
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</fields>
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</register>
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<register>
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<name>SFR_CGUFD_CFGFDCR1</name>
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<name>SFR_CGUFD_CFGFDCR_0_4_1</name>
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<addressOffset>0x0018</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>cfgfdcr1</name>
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<name>cfgfdcr_0_4_1</name>
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<msb>15</msb>
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<bitRange>[15:0]</bitRange>
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<lsb>0</lsb>
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@ -7346,13 +7506,13 @@ position to clear the flag]]></description>
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</fields>
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</register>
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<register>
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<name>SFR_CGUFD_CFGFDCR2</name>
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<name>SFR_CGUFD_CFGFDCR_0_4_2</name>
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<addressOffset>0x001c</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>cfgfdcr2</name>
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<name>cfgfdcr_0_4_2</name>
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<msb>15</msb>
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<bitRange>[15:0]</bitRange>
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<lsb>0</lsb>
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@ -7361,13 +7521,13 @@ position to clear the flag]]></description>
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</fields>
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</register>
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<register>
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<name>SFR_CGUFD_CFGFDCR3</name>
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<name>SFR_CGUFD_CFGFDCR_0_4_3</name>
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<addressOffset>0x0020</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>cfgfdcr3</name>
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<name>cfgfdcr_0_4_3</name>
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<msb>15</msb>
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<bitRange>[15:0]</bitRange>
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<lsb>0</lsb>
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@ -7376,13 +7536,28 @@ position to clear the flag]]></description>
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</fields>
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</register>
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<register>
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<name>SFR_CGUFD_CFGFDCR4</name>
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<name>SFR_CGUFD_CFGFDCR_0_4_4</name>
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<addressOffset>0x0024</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>cfgfdcr4</name>
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<name>cfgfdcr_0_4_4</name>
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<msb>15</msb>
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<bitRange>[15:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[cfgfdcr read/write control register]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>SFR_CGUFDAO</name>
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<addressOffset>0x0028</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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||||
<fields>
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<field>
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<name>cfgfdcr</name>
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<msb>15</msb>
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<bitRange>[15:0]</bitRange>
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<lsb>0</lsb>
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||||
|
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@ -7420,6 +7595,21 @@ position to clear the flag]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>SFR_CGUFDPKE</name>
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<addressOffset>0x0034</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>sfr_cgufdpke</name>
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<msb>8</msb>
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<bitRange>[8:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[sfr_cgufdpke read/write control register]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>SFR_CGUFSSR_FSFREQ0</name>
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<addressOffset>0x0040</addressOffset>
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||||
|
|
@ -12664,6 +12854,108 @@ position to clear the flag]]></description>
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|||
<usage>registers</usage>
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</addressBlock>
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</peripheral>
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<peripheral>
|
||||
<name>CORESUB_SRAMTRM</name>
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||||
<baseAddress>0x40014000</baseAddress>
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<groupName>CORESUB_SRAMTRM</groupName>
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||||
<registers>
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<register>
|
||||
<name>SFR_CACHE</name>
|
||||
<addressOffset>0x0000</addressOffset>
|
||||
<resetValue>0x00</resetValue>
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||||
<size>32</size>
|
||||
<fields>
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<field>
|
||||
<name>sfr_cache</name>
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||||
<msb>2</msb>
|
||||
<bitRange>[2:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[sfr_cache read/write control register]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SFR_ITCM</name>
|
||||
<addressOffset>0x0004</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>sfr_itcm</name>
|
||||
<msb>4</msb>
|
||||
<bitRange>[4:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[sfr_itcm read/write control register]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SFR_DTCM</name>
|
||||
<addressOffset>0x0008</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>sfr_dtcm</name>
|
||||
<msb>4</msb>
|
||||
<bitRange>[4:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[sfr_dtcm read/write control register]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SFR_SRAM0</name>
|
||||
<addressOffset>0x000c</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>sfr_sram0</name>
|
||||
<msb>4</msb>
|
||||
<bitRange>[4:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[sfr_sram0 read/write control register]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SFR_SRAM1</name>
|
||||
<addressOffset>0x0010</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>sfr_sram1</name>
|
||||
<msb>4</msb>
|
||||
<bitRange>[4:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[sfr_sram1 read/write control register]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SFR_VEXRAM</name>
|
||||
<addressOffset>0x0014</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>sfr_vexram</name>
|
||||
<msb>2</msb>
|
||||
<bitRange>[2:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[sfr_vexram read/write control register]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x18</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>MDMA</name>
|
||||
<baseAddress>0x40012000</baseAddress>
|
||||
|
|
@ -13656,11 +13948,27 @@ position to clear the flag]]></description>
|
|||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>sr_vdsr</name>
|
||||
<name>vdflag</name>
|
||||
<msb>7</msb>
|
||||
<bitRange>[7:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[sr_vdsr read only status register]]></description>
|
||||
<description><![CDATA[vdflag read only status register]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SFR_VDFR</name>
|
||||
<addressOffset>0x000c</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>vdflag</name>
|
||||
<msb>7</msb>
|
||||
<bitRange>[7:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[vdflag flag register. `1` means event happened, write back `1` in respective bit
|
||||
position to clear the flag]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
|
|
@ -13829,10 +14137,70 @@ position to clear the flag]]></description>
|
|||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SFR_VDIP_ENA</name>
|
||||
<addressOffset>0x0040</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>vdena</name>
|
||||
<msb>3</msb>
|
||||
<bitRange>[3:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[vdena read/write control register]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SFR_VDIP_TEST</name>
|
||||
<addressOffset>0x0044</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>vdtst</name>
|
||||
<msb>7</msb>
|
||||
<bitRange>[7:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[vdtst read/write control register]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SFR_LDIP_TEST</name>
|
||||
<addressOffset>0x0048</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>ldtst</name>
|
||||
<msb>3</msb>
|
||||
<bitRange>[3:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[ldtst read/write control register]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SFR_LDIP_FD</name>
|
||||
<addressOffset>0x004c</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>sfr_ldip_fd</name>
|
||||
<msb>15</msb>
|
||||
<bitRange>[15:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[sfr_ldip_fd read/write control register]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x40</size>
|
||||
<size>0x50</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
</peripheral>
|
||||
|
|
@ -14339,12 +14707,12 @@ position to clear the flag]]></description>
|
|||
<memoryRegion>
|
||||
<name>SEG_PCON</name>
|
||||
<baseAddress>0x40020800</baseAddress>
|
||||
<size>0x00000100</size>
|
||||
<size>0x00000000</size>
|
||||
</memoryRegion>
|
||||
<memoryRegion>
|
||||
<name>SEG_PKB</name>
|
||||
<baseAddress>0x40020900</baseAddress>
|
||||
<size>0x00000100</size>
|
||||
<baseAddress>0x40020800</baseAddress>
|
||||
<size>0x00000200</size>
|
||||
</memoryRegion>
|
||||
<memoryRegion>
|
||||
<name>SEG_PIB</name>
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
|
||||
<vendor>litex</vendor>
|
||||
<name>SOC</name>
|
||||
<description><![CDATA[Litex SoC 2023-08-20 16:58:49]]></description>
|
||||
<description><![CDATA[Litex SoC 2023-09-15 20:42:27]]></description>
|
||||
|
||||
<addressUnitBits>8</addressUnitBits>
|
||||
<width>32</width>
|
||||
|
|
|
|||
|
|
@ -278,9 +278,9 @@ pub const HW_SEG_HOUT_MEM_LEN: usize = 256;
|
|||
pub const HW_SEG_SOB_MEM: usize = 0x40020700;
|
||||
pub const HW_SEG_SOB_MEM_LEN: usize = 256;
|
||||
pub const HW_SEG_PCON_MEM: usize = 0x40020800;
|
||||
pub const HW_SEG_PCON_MEM_LEN: usize = 256;
|
||||
pub const HW_SEG_PKB_MEM: usize = 0x40020900;
|
||||
pub const HW_SEG_PKB_MEM_LEN: usize = 256;
|
||||
pub const HW_SEG_PCON_MEM_LEN: usize = 0;
|
||||
pub const HW_SEG_PKB_MEM: usize = 0x40020800;
|
||||
pub const HW_SEG_PKB_MEM_LEN: usize = 512;
|
||||
pub const HW_SEG_PIB_MEM: usize = 0x40020a00;
|
||||
pub const HW_SEG_PIB_MEM_LEN: usize = 1024;
|
||||
pub const HW_SEG_PSIB_MEM: usize = 0x40020e00;
|
||||
|
|
@ -400,6 +400,7 @@ pub const HW_IOX_BASE : usize = 0x5012f000;
|
|||
pub const HW_PWM_BASE : usize = 0x50120000;
|
||||
pub const HW_SDDC_BASE : usize = 0x50121000;
|
||||
pub const HW_RP_PIO_BASE : usize = 0x50123000;
|
||||
pub const HW_CORESUB_SRAMTRM_BASE : usize = 0x40014000;
|
||||
pub const HW_MDMA_BASE : usize = 0x40012000;
|
||||
pub const HW_QFC_BASE : usize = 0x40010000;
|
||||
pub const HW_MBOX_APB_BASE : usize = 0x40013000;
|
||||
|
|
@ -3286,7 +3287,7 @@ pub mod utra {
|
|||
}
|
||||
|
||||
pub mod aes {
|
||||
pub const AES_NUMREGS: usize = 10;
|
||||
pub const AES_NUMREGS: usize = 11;
|
||||
|
||||
pub const SFR_CRFUNC: crate::Register = crate::Register::new(0, 0xff);
|
||||
pub const SFR_CRFUNC_SFR_CRFUNC: crate::Field = crate::Field::new(8, 0, SFR_CRFUNC);
|
||||
|
|
@ -3311,6 +3312,9 @@ pub mod utra {
|
|||
pub const SFR_OPT1: crate::Register = crate::Register::new(5, 0xffff);
|
||||
pub const SFR_OPT1_SFR_OPT1: crate::Field = crate::Field::new(16, 0, SFR_OPT1);
|
||||
|
||||
pub const SFR_OPTLTX: crate::Register = crate::Register::new(6, 0xf);
|
||||
pub const SFR_OPTLTX_SFR_OPTLTX: crate::Field = crate::Field::new(4, 0, SFR_OPTLTX);
|
||||
|
||||
pub const SFR_SEGPTR_PTRID_IV: crate::Register = crate::Register::new(12, 0xfff);
|
||||
pub const SFR_SEGPTR_PTRID_IV_PTRID_IV: crate::Field = crate::Field::new(12, 0, SFR_SEGPTR_PTRID_IV);
|
||||
|
||||
|
|
@ -3327,7 +3331,7 @@ pub mod utra {
|
|||
}
|
||||
|
||||
pub mod combohash {
|
||||
pub const COMBOHASH_NUMREGS: usize = 13;
|
||||
pub const COMBOHASH_NUMREGS: usize = 14;
|
||||
|
||||
pub const SFR_CRFUNC: crate::Register = crate::Register::new(0, 0xff);
|
||||
pub const SFR_CRFUNC_CR_FUNC: crate::Field = crate::Field::new(8, 0, SFR_CRFUNC);
|
||||
|
|
@ -3338,11 +3342,13 @@ pub mod utra {
|
|||
pub const SFR_SRMFSM: crate::Register = crate::Register::new(2, 0xff);
|
||||
pub const SFR_SRMFSM_MFSM: crate::Field = crate::Field::new(8, 0, SFR_SRMFSM);
|
||||
|
||||
pub const SFR_FR: crate::Register = crate::Register::new(3, 0xf);
|
||||
pub const SFR_FR: crate::Register = crate::Register::new(3, 0x3f);
|
||||
pub const SFR_FR_MFSM_DONE: crate::Field = crate::Field::new(1, 0, SFR_FR);
|
||||
pub const SFR_FR_HASH_DONE: crate::Field = crate::Field::new(1, 1, SFR_FR);
|
||||
pub const SFR_FR_CHNLO_DONE: crate::Field = crate::Field::new(1, 2, SFR_FR);
|
||||
pub const SFR_FR_CHNLI_DONE: crate::Field = crate::Field::new(1, 3, SFR_FR);
|
||||
pub const SFR_FR_CHKDONE: crate::Field = crate::Field::new(1, 4, SFR_FR);
|
||||
pub const SFR_FR_CHKPASS: crate::Field = crate::Field::new(1, 5, SFR_FR);
|
||||
|
||||
pub const SFR_OPT1: crate::Register = crate::Register::new(4, 0xffff);
|
||||
pub const SFR_OPT1_CR_OPT_HASHCNT: crate::Field = crate::Field::new(16, 0, SFR_OPT1);
|
||||
|
|
@ -3355,6 +3361,9 @@ pub mod utra {
|
|||
pub const SFR_OPT3: crate::Register = crate::Register::new(6, 0xff);
|
||||
pub const SFR_OPT3_SFR_OPT3: crate::Field = crate::Field::new(8, 0, SFR_OPT3);
|
||||
|
||||
pub const SFR_BLKT0: crate::Register = crate::Register::new(7, 0xff);
|
||||
pub const SFR_BLKT0_SFR_BLKT0: crate::Field = crate::Field::new(8, 0, SFR_BLKT0);
|
||||
|
||||
pub const SFR_SEGPTR_SEGID_LKEY: crate::Register = crate::Register::new(8, 0xfff);
|
||||
pub const SFR_SEGPTR_SEGID_LKEY_SEGID_LKEY: crate::Field = crate::Field::new(12, 0, SFR_SEGPTR_SEGID_LKEY);
|
||||
|
||||
|
|
@ -3370,17 +3379,18 @@ pub mod utra {
|
|||
pub const SFR_SEGPTR_SEGID_HOUT: crate::Register = crate::Register::new(13, 0xfff);
|
||||
pub const SFR_SEGPTR_SEGID_HOUT_SEGID_HOUT: crate::Field = crate::Field::new(12, 0, SFR_SEGPTR_SEGID_HOUT);
|
||||
|
||||
pub const SFR_SEGPTR_SEGID_SOB: crate::Register = crate::Register::new(14, 0xfff);
|
||||
pub const SFR_SEGPTR_SEGID_SOB_SEGID_SOB: crate::Field = crate::Field::new(12, 0, SFR_SEGPTR_SEGID_SOB);
|
||||
pub const SFR_SEGPTR_SEGID_HOUT2: crate::Register = crate::Register::new(15, 0xfff);
|
||||
pub const SFR_SEGPTR_SEGID_HOUT2_SEGID_HOUT2: crate::Field = crate::Field::new(12, 0, SFR_SEGPTR_SEGID_HOUT2);
|
||||
|
||||
pub const HW_COMBOHASH_BASE: usize = 0x4002b000;
|
||||
}
|
||||
|
||||
pub mod pke {
|
||||
pub const PKE_NUMREGS: usize = 12;
|
||||
pub const PKE_NUMREGS: usize = 14;
|
||||
|
||||
pub const SFR_CRFUNC: crate::Register = crate::Register::new(0, 0xff);
|
||||
pub const SFR_CRFUNC_SFR_CRFUNC: crate::Field = crate::Field::new(8, 0, SFR_CRFUNC);
|
||||
pub const SFR_CRFUNC: crate::Register = crate::Register::new(0, 0xffff);
|
||||
pub const SFR_CRFUNC_CR_FUNC: crate::Field = crate::Field::new(8, 0, SFR_CRFUNC);
|
||||
pub const SFR_CRFUNC_CR_PCOREIR: crate::Field = crate::Field::new(8, 8, SFR_CRFUNC);
|
||||
|
||||
pub const SFR_AR: crate::Register = crate::Register::new(1, 0xffffffff);
|
||||
pub const SFR_AR_SFR_AR: crate::Field = crate::Field::new(32, 0, SFR_AR);
|
||||
|
|
@ -3402,6 +3412,12 @@ pub mod utra {
|
|||
pub const SFR_OPTEW: crate::Register = crate::Register::new(5, 0x1fff);
|
||||
pub const SFR_OPTEW_SFR_OPTEW: crate::Field = crate::Field::new(13, 0, SFR_OPTEW);
|
||||
|
||||
pub const SFR_OPTRW: crate::Register = crate::Register::new(6, 0x3ff);
|
||||
pub const SFR_OPTRW_SFR_OPTRW: crate::Field = crate::Field::new(10, 0, SFR_OPTRW);
|
||||
|
||||
pub const SFR_OPTLTX: crate::Register = crate::Register::new(7, 0x1f);
|
||||
pub const SFR_OPTLTX_SFR_OPTLTX: crate::Field = crate::Field::new(5, 0, SFR_OPTLTX);
|
||||
|
||||
pub const SFR_OPTMASK: crate::Register = crate::Register::new(8, 0xffff);
|
||||
pub const SFR_OPTMASK_SFR_OPTMASK: crate::Field = crate::Field::new(16, 0, SFR_OPTMASK);
|
||||
|
||||
|
|
@ -3484,7 +3500,7 @@ pub mod utra {
|
|||
}
|
||||
|
||||
pub mod sce_glbsfr {
|
||||
pub const SCE_GLBSFR_NUMREGS: usize = 17;
|
||||
pub const SCE_GLBSFR_NUMREGS: usize = 18;
|
||||
|
||||
pub const SFR_SCEMODE: crate::Register = crate::Register::new(0, 0x3);
|
||||
pub const SFR_SCEMODE_CR_SCEMODE: crate::Field = crate::Field::new(2, 0, SFR_SCEMODE);
|
||||
|
|
@ -3507,8 +3523,8 @@ pub mod utra {
|
|||
pub const SFR_ARCLR: crate::Register = crate::Register::new(7, 0xffffffff);
|
||||
pub const SFR_ARCLR_AR_CLRRAM: crate::Field = crate::Field::new(32, 0, SFR_ARCLR);
|
||||
|
||||
pub const SFR_TICKCYC: crate::Register = crate::Register::new(8, 0xff);
|
||||
pub const SFR_TICKCYC_SFR_TICKCYC: crate::Field = crate::Field::new(8, 0, SFR_TICKCYC);
|
||||
pub const SFR_FRACERR: crate::Register = crate::Register::new(8, 0xff);
|
||||
pub const SFR_FRACERR_FR_ACERR: crate::Field = crate::Field::new(8, 0, SFR_FRACERR);
|
||||
|
||||
pub const SFR_TICKCNT: crate::Register = crate::Register::new(9, 0xffffffff);
|
||||
pub const SFR_TICKCNT_SFR_TICKCNT: crate::Field = crate::Field::new(32, 0, SFR_TICKCNT);
|
||||
|
|
@ -3537,17 +3553,20 @@ pub mod utra {
|
|||
pub const SFR_FFCNT_SR_FF5: crate::Register = crate::Register::new(21, 0xffff);
|
||||
pub const SFR_FFCNT_SR_FF5_SR_FF5: crate::Field = crate::Field::new(16, 0, SFR_FFCNT_SR_FF5);
|
||||
|
||||
pub const SFR_TS: crate::Register = crate::Register::new(63, 0xffff);
|
||||
pub const SFR_TS_CR_TS: crate::Field = crate::Field::new(16, 0, SFR_TS);
|
||||
|
||||
pub const HW_SCE_GLBSFR_BASE: usize = 0x40028000;
|
||||
}
|
||||
|
||||
pub mod trng {
|
||||
pub const TRNG_NUMREGS: usize = 5;
|
||||
pub const TRNG_NUMREGS: usize = 9;
|
||||
|
||||
pub const SFR_CRSRC: crate::Register = crate::Register::new(0, 0xfff);
|
||||
pub const SFR_CRSRC_SFR_CRSRC: crate::Field = crate::Field::new(12, 0, SFR_CRSRC);
|
||||
|
||||
pub const SFR_AR_STOP: crate::Register = crate::Register::new(1, 0xffffffff);
|
||||
pub const SFR_AR_STOP_SFR_AR_STOP: crate::Field = crate::Field::new(32, 0, SFR_AR_STOP);
|
||||
pub const SFR_CRANA: crate::Register = crate::Register::new(1, 0xffff);
|
||||
pub const SFR_CRANA_SFR_CRANA: crate::Field = crate::Field::new(16, 0, SFR_CRANA);
|
||||
|
||||
pub const SFR_PP: crate::Register = crate::Register::new(2, 0x1ffff);
|
||||
pub const SFR_PP_SFR_PP: crate::Field = crate::Field::new(17, 0, SFR_PP);
|
||||
|
|
@ -3558,6 +3577,18 @@ pub mod utra {
|
|||
pub const SFR_SR: crate::Register = crate::Register::new(4, 0xffffffff);
|
||||
pub const SFR_SR_SR_RNG: crate::Field = crate::Field::new(32, 0, SFR_SR);
|
||||
|
||||
pub const SFR_AR_GEN: crate::Register = crate::Register::new(5, 0xffffffff);
|
||||
pub const SFR_AR_GEN_SFR_AR_GEN: crate::Field = crate::Field::new(32, 0, SFR_AR_GEN);
|
||||
|
||||
pub const SFR_FR: crate::Register = crate::Register::new(6, 0x3);
|
||||
pub const SFR_FR_SFR_FR: crate::Field = crate::Field::new(2, 0, SFR_FR);
|
||||
|
||||
pub const SFR_CHAIN_RNGCHAINEN0: crate::Register = crate::Register::new(16, 0xffffffff);
|
||||
pub const SFR_CHAIN_RNGCHAINEN0_RNGCHAINEN0: crate::Field = crate::Field::new(32, 0, SFR_CHAIN_RNGCHAINEN0);
|
||||
|
||||
pub const SFR_CHAIN_RNGCHAINEN1: crate::Register = crate::Register::new(17, 0xffffffff);
|
||||
pub const SFR_CHAIN_RNGCHAINEN1_RNGCHAINEN1: crate::Field = crate::Field::new(32, 0, SFR_CHAIN_RNGCHAINEN1);
|
||||
|
||||
pub const HW_TRNG_BASE: usize = 0x4002e000;
|
||||
}
|
||||
|
||||
|
|
@ -3670,7 +3701,7 @@ pub mod utra {
|
|||
}
|
||||
|
||||
pub mod sysctrl {
|
||||
pub const SYSCTRL_NUMREGS: usize = 31;
|
||||
pub const SYSCTRL_NUMREGS: usize = 33;
|
||||
|
||||
pub const SFR_CGUSEC: crate::Register = crate::Register::new(0, 0xffff);
|
||||
pub const SFR_CGUSEC_SFR_CGUSEC: crate::Field = crate::Field::new(16, 0, SFR_CGUSEC);
|
||||
|
|
@ -3681,20 +3712,23 @@ pub mod utra {
|
|||
pub const SFR_CGUSEL0: crate::Register = crate::Register::new(4, 0x3);
|
||||
pub const SFR_CGUSEL0_SFR_CGUSEL0: crate::Field = crate::Field::new(2, 0, SFR_CGUSEL0);
|
||||
|
||||
pub const SFR_CGUFD_CFGFDCR0: crate::Register = crate::Register::new(5, 0xffff);
|
||||
pub const SFR_CGUFD_CFGFDCR0_CFGFDCR0: crate::Field = crate::Field::new(16, 0, SFR_CGUFD_CFGFDCR0);
|
||||
pub const SFR_CGUFD_CFGFDCR_0_4_0: crate::Register = crate::Register::new(5, 0xffff);
|
||||
pub const SFR_CGUFD_CFGFDCR_0_4_0_CFGFDCR_0_4_0: crate::Field = crate::Field::new(16, 0, SFR_CGUFD_CFGFDCR_0_4_0);
|
||||
|
||||
pub const SFR_CGUFD_CFGFDCR1: crate::Register = crate::Register::new(6, 0xffff);
|
||||
pub const SFR_CGUFD_CFGFDCR1_CFGFDCR1: crate::Field = crate::Field::new(16, 0, SFR_CGUFD_CFGFDCR1);
|
||||
pub const SFR_CGUFD_CFGFDCR_0_4_1: crate::Register = crate::Register::new(6, 0xffff);
|
||||
pub const SFR_CGUFD_CFGFDCR_0_4_1_CFGFDCR_0_4_1: crate::Field = crate::Field::new(16, 0, SFR_CGUFD_CFGFDCR_0_4_1);
|
||||
|
||||
pub const SFR_CGUFD_CFGFDCR2: crate::Register = crate::Register::new(7, 0xffff);
|
||||
pub const SFR_CGUFD_CFGFDCR2_CFGFDCR2: crate::Field = crate::Field::new(16, 0, SFR_CGUFD_CFGFDCR2);
|
||||
pub const SFR_CGUFD_CFGFDCR_0_4_2: crate::Register = crate::Register::new(7, 0xffff);
|
||||
pub const SFR_CGUFD_CFGFDCR_0_4_2_CFGFDCR_0_4_2: crate::Field = crate::Field::new(16, 0, SFR_CGUFD_CFGFDCR_0_4_2);
|
||||
|
||||
pub const SFR_CGUFD_CFGFDCR3: crate::Register = crate::Register::new(8, 0xffff);
|
||||
pub const SFR_CGUFD_CFGFDCR3_CFGFDCR3: crate::Field = crate::Field::new(16, 0, SFR_CGUFD_CFGFDCR3);
|
||||
pub const SFR_CGUFD_CFGFDCR_0_4_3: crate::Register = crate::Register::new(8, 0xffff);
|
||||
pub const SFR_CGUFD_CFGFDCR_0_4_3_CFGFDCR_0_4_3: crate::Field = crate::Field::new(16, 0, SFR_CGUFD_CFGFDCR_0_4_3);
|
||||
|
||||
pub const SFR_CGUFD_CFGFDCR4: crate::Register = crate::Register::new(9, 0xffff);
|
||||
pub const SFR_CGUFD_CFGFDCR4_CFGFDCR4: crate::Field = crate::Field::new(16, 0, SFR_CGUFD_CFGFDCR4);
|
||||
pub const SFR_CGUFD_CFGFDCR_0_4_4: crate::Register = crate::Register::new(9, 0xffff);
|
||||
pub const SFR_CGUFD_CFGFDCR_0_4_4_CFGFDCR_0_4_4: crate::Field = crate::Field::new(16, 0, SFR_CGUFD_CFGFDCR_0_4_4);
|
||||
|
||||
pub const SFR_CGUFDAO: crate::Register = crate::Register::new(10, 0xffff);
|
||||
pub const SFR_CGUFDAO_CFGFDCR: crate::Field = crate::Field::new(16, 0, SFR_CGUFDAO);
|
||||
|
||||
pub const SFR_CGUSET: crate::Register = crate::Register::new(11, 0xffffffff);
|
||||
pub const SFR_CGUSET_SFR_CGUSET: crate::Field = crate::Field::new(32, 0, SFR_CGUSET);
|
||||
|
|
@ -3702,6 +3736,9 @@ pub mod utra {
|
|||
pub const SFR_CGUSEL1: crate::Register = crate::Register::new(12, 0x1);
|
||||
pub const SFR_CGUSEL1_SFR_CGUSEL1: crate::Field = crate::Field::new(1, 0, SFR_CGUSEL1);
|
||||
|
||||
pub const SFR_CGUFDPKE: crate::Register = crate::Register::new(13, 0x1ff);
|
||||
pub const SFR_CGUFDPKE_SFR_CGUFDPKE: crate::Field = crate::Field::new(9, 0, SFR_CGUFDPKE);
|
||||
|
||||
pub const SFR_CGUFSSR_FSFREQ0: crate::Register = crate::Register::new(16, 0xffff);
|
||||
pub const SFR_CGUFSSR_FSFREQ0_FSFREQ0: crate::Field = crate::Field::new(16, 0, SFR_CGUFSSR_FSFREQ0);
|
||||
|
||||
|
|
@ -4704,6 +4741,30 @@ pub mod utra {
|
|||
pub const HW_RP_PIO_BASE: usize = 0x50123000;
|
||||
}
|
||||
|
||||
pub mod coresub_sramtrm {
|
||||
pub const CORESUB_SRAMTRM_NUMREGS: usize = 6;
|
||||
|
||||
pub const SFR_CACHE: crate::Register = crate::Register::new(0, 0x7);
|
||||
pub const SFR_CACHE_SFR_CACHE: crate::Field = crate::Field::new(3, 0, SFR_CACHE);
|
||||
|
||||
pub const SFR_ITCM: crate::Register = crate::Register::new(1, 0x1f);
|
||||
pub const SFR_ITCM_SFR_ITCM: crate::Field = crate::Field::new(5, 0, SFR_ITCM);
|
||||
|
||||
pub const SFR_DTCM: crate::Register = crate::Register::new(2, 0x1f);
|
||||
pub const SFR_DTCM_SFR_DTCM: crate::Field = crate::Field::new(5, 0, SFR_DTCM);
|
||||
|
||||
pub const SFR_SRAM0: crate::Register = crate::Register::new(3, 0x1f);
|
||||
pub const SFR_SRAM0_SFR_SRAM0: crate::Field = crate::Field::new(5, 0, SFR_SRAM0);
|
||||
|
||||
pub const SFR_SRAM1: crate::Register = crate::Register::new(4, 0x1f);
|
||||
pub const SFR_SRAM1_SFR_SRAM1: crate::Field = crate::Field::new(5, 0, SFR_SRAM1);
|
||||
|
||||
pub const SFR_VEXRAM: crate::Register = crate::Register::new(5, 0x7);
|
||||
pub const SFR_VEXRAM_SFR_VEXRAM: crate::Field = crate::Field::new(3, 0, SFR_VEXRAM);
|
||||
|
||||
pub const HW_CORESUB_SRAMTRM_BASE: usize = 0x40014000;
|
||||
}
|
||||
|
||||
pub mod mdma {
|
||||
pub const MDMA_NUMREGS: usize = 24;
|
||||
|
||||
|
|
@ -4911,7 +4972,7 @@ pub mod utra {
|
|||
}
|
||||
|
||||
pub mod sensorc {
|
||||
pub const SENSORC_NUMREGS: usize = 14;
|
||||
pub const SENSORC_NUMREGS: usize = 19;
|
||||
|
||||
pub const SFR_VDMASK0: crate::Register = crate::Register::new(0, 0xff);
|
||||
pub const SFR_VDMASK0_CR_VDMASK0: crate::Field = crate::Field::new(8, 0, SFR_VDMASK0);
|
||||
|
|
@ -4920,7 +4981,10 @@ pub mod utra {
|
|||
pub const SFR_VDMASK1_CR_VDMASK1: crate::Field = crate::Field::new(8, 0, SFR_VDMASK1);
|
||||
|
||||
pub const SFR_VDSR: crate::Register = crate::Register::new(2, 0xff);
|
||||
pub const SFR_VDSR_SR_VDSR: crate::Field = crate::Field::new(8, 0, SFR_VDSR);
|
||||
pub const SFR_VDSR_VDFLAG: crate::Field = crate::Field::new(8, 0, SFR_VDSR);
|
||||
|
||||
pub const SFR_VDFR: crate::Register = crate::Register::new(3, 0xff);
|
||||
pub const SFR_VDFR_VDFLAG: crate::Field = crate::Field::new(8, 0, SFR_VDFR);
|
||||
|
||||
pub const SFR_LDMASK: crate::Register = crate::Register::new(4, 0xf);
|
||||
pub const SFR_LDMASK_CR_LDMASK: crate::Field = crate::Field::new(4, 0, SFR_LDMASK);
|
||||
|
|
@ -4955,6 +5019,18 @@ pub mod utra {
|
|||
pub const SFR_VDCFG_CR_VDCFG7: crate::Register = crate::Register::new(15, 0xf);
|
||||
pub const SFR_VDCFG_CR_VDCFG7_CR_VDCFG7: crate::Field = crate::Field::new(4, 0, SFR_VDCFG_CR_VDCFG7);
|
||||
|
||||
pub const SFR_VDIP_ENA: crate::Register = crate::Register::new(16, 0xf);
|
||||
pub const SFR_VDIP_ENA_VDENA: crate::Field = crate::Field::new(4, 0, SFR_VDIP_ENA);
|
||||
|
||||
pub const SFR_VDIP_TEST: crate::Register = crate::Register::new(17, 0xff);
|
||||
pub const SFR_VDIP_TEST_VDTST: crate::Field = crate::Field::new(8, 0, SFR_VDIP_TEST);
|
||||
|
||||
pub const SFR_LDIP_TEST: crate::Register = crate::Register::new(18, 0xf);
|
||||
pub const SFR_LDIP_TEST_LDTST: crate::Field = crate::Field::new(4, 0, SFR_LDIP_TEST);
|
||||
|
||||
pub const SFR_LDIP_FD: crate::Register = crate::Register::new(19, 0xffff);
|
||||
pub const SFR_LDIP_FD_SFR_LDIP_FD: crate::Field = crate::Field::new(16, 0, SFR_LDIP_FD);
|
||||
|
||||
pub const HW_SENSORC_BASE: usize = 0x40053000;
|
||||
}
|
||||
}
|
||||
|
|
@ -14836,6 +14912,14 @@ mod tests {
|
|||
baz |= aes_csr.ms(utra::aes::SFR_OPT1_SFR_OPT1, 1);
|
||||
aes_csr.wfo(utra::aes::SFR_OPT1_SFR_OPT1, baz);
|
||||
|
||||
let foo = aes_csr.r(utra::aes::SFR_OPTLTX);
|
||||
aes_csr.wo(utra::aes::SFR_OPTLTX, foo);
|
||||
let bar = aes_csr.rf(utra::aes::SFR_OPTLTX_SFR_OPTLTX);
|
||||
aes_csr.rmwf(utra::aes::SFR_OPTLTX_SFR_OPTLTX, bar);
|
||||
let mut baz = aes_csr.zf(utra::aes::SFR_OPTLTX_SFR_OPTLTX, bar);
|
||||
baz |= aes_csr.ms(utra::aes::SFR_OPTLTX_SFR_OPTLTX, 1);
|
||||
aes_csr.wfo(utra::aes::SFR_OPTLTX_SFR_OPTLTX, baz);
|
||||
|
||||
let foo = aes_csr.r(utra::aes::SFR_SEGPTR_PTRID_IV);
|
||||
aes_csr.wo(utra::aes::SFR_SEGPTR_PTRID_IV, foo);
|
||||
let bar = aes_csr.rf(utra::aes::SFR_SEGPTR_PTRID_IV_PTRID_IV);
|
||||
|
|
@ -14921,6 +15005,16 @@ mod tests {
|
|||
let mut baz = combohash_csr.zf(utra::combohash::SFR_FR_CHNLI_DONE, bar);
|
||||
baz |= combohash_csr.ms(utra::combohash::SFR_FR_CHNLI_DONE, 1);
|
||||
combohash_csr.wfo(utra::combohash::SFR_FR_CHNLI_DONE, baz);
|
||||
let bar = combohash_csr.rf(utra::combohash::SFR_FR_CHKDONE);
|
||||
combohash_csr.rmwf(utra::combohash::SFR_FR_CHKDONE, bar);
|
||||
let mut baz = combohash_csr.zf(utra::combohash::SFR_FR_CHKDONE, bar);
|
||||
baz |= combohash_csr.ms(utra::combohash::SFR_FR_CHKDONE, 1);
|
||||
combohash_csr.wfo(utra::combohash::SFR_FR_CHKDONE, baz);
|
||||
let bar = combohash_csr.rf(utra::combohash::SFR_FR_CHKPASS);
|
||||
combohash_csr.rmwf(utra::combohash::SFR_FR_CHKPASS, bar);
|
||||
let mut baz = combohash_csr.zf(utra::combohash::SFR_FR_CHKPASS, bar);
|
||||
baz |= combohash_csr.ms(utra::combohash::SFR_FR_CHKPASS, 1);
|
||||
combohash_csr.wfo(utra::combohash::SFR_FR_CHKPASS, baz);
|
||||
|
||||
let foo = combohash_csr.r(utra::combohash::SFR_OPT1);
|
||||
combohash_csr.wo(utra::combohash::SFR_OPT1, foo);
|
||||
|
|
@ -14956,6 +15050,14 @@ mod tests {
|
|||
baz |= combohash_csr.ms(utra::combohash::SFR_OPT3_SFR_OPT3, 1);
|
||||
combohash_csr.wfo(utra::combohash::SFR_OPT3_SFR_OPT3, baz);
|
||||
|
||||
let foo = combohash_csr.r(utra::combohash::SFR_BLKT0);
|
||||
combohash_csr.wo(utra::combohash::SFR_BLKT0, foo);
|
||||
let bar = combohash_csr.rf(utra::combohash::SFR_BLKT0_SFR_BLKT0);
|
||||
combohash_csr.rmwf(utra::combohash::SFR_BLKT0_SFR_BLKT0, bar);
|
||||
let mut baz = combohash_csr.zf(utra::combohash::SFR_BLKT0_SFR_BLKT0, bar);
|
||||
baz |= combohash_csr.ms(utra::combohash::SFR_BLKT0_SFR_BLKT0, 1);
|
||||
combohash_csr.wfo(utra::combohash::SFR_BLKT0_SFR_BLKT0, baz);
|
||||
|
||||
let foo = combohash_csr.r(utra::combohash::SFR_SEGPTR_SEGID_LKEY);
|
||||
combohash_csr.wo(utra::combohash::SFR_SEGPTR_SEGID_LKEY, foo);
|
||||
let bar = combohash_csr.rf(utra::combohash::SFR_SEGPTR_SEGID_LKEY_SEGID_LKEY);
|
||||
|
|
@ -14996,13 +15098,13 @@ mod tests {
|
|||
baz |= combohash_csr.ms(utra::combohash::SFR_SEGPTR_SEGID_HOUT_SEGID_HOUT, 1);
|
||||
combohash_csr.wfo(utra::combohash::SFR_SEGPTR_SEGID_HOUT_SEGID_HOUT, baz);
|
||||
|
||||
let foo = combohash_csr.r(utra::combohash::SFR_SEGPTR_SEGID_SOB);
|
||||
combohash_csr.wo(utra::combohash::SFR_SEGPTR_SEGID_SOB, foo);
|
||||
let bar = combohash_csr.rf(utra::combohash::SFR_SEGPTR_SEGID_SOB_SEGID_SOB);
|
||||
combohash_csr.rmwf(utra::combohash::SFR_SEGPTR_SEGID_SOB_SEGID_SOB, bar);
|
||||
let mut baz = combohash_csr.zf(utra::combohash::SFR_SEGPTR_SEGID_SOB_SEGID_SOB, bar);
|
||||
baz |= combohash_csr.ms(utra::combohash::SFR_SEGPTR_SEGID_SOB_SEGID_SOB, 1);
|
||||
combohash_csr.wfo(utra::combohash::SFR_SEGPTR_SEGID_SOB_SEGID_SOB, baz);
|
||||
let foo = combohash_csr.r(utra::combohash::SFR_SEGPTR_SEGID_HOUT2);
|
||||
combohash_csr.wo(utra::combohash::SFR_SEGPTR_SEGID_HOUT2, foo);
|
||||
let bar = combohash_csr.rf(utra::combohash::SFR_SEGPTR_SEGID_HOUT2_SEGID_HOUT2);
|
||||
combohash_csr.rmwf(utra::combohash::SFR_SEGPTR_SEGID_HOUT2_SEGID_HOUT2, bar);
|
||||
let mut baz = combohash_csr.zf(utra::combohash::SFR_SEGPTR_SEGID_HOUT2_SEGID_HOUT2, bar);
|
||||
baz |= combohash_csr.ms(utra::combohash::SFR_SEGPTR_SEGID_HOUT2_SEGID_HOUT2, 1);
|
||||
combohash_csr.wfo(utra::combohash::SFR_SEGPTR_SEGID_HOUT2_SEGID_HOUT2, baz);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -15013,11 +15115,16 @@ mod tests {
|
|||
|
||||
let foo = pke_csr.r(utra::pke::SFR_CRFUNC);
|
||||
pke_csr.wo(utra::pke::SFR_CRFUNC, foo);
|
||||
let bar = pke_csr.rf(utra::pke::SFR_CRFUNC_SFR_CRFUNC);
|
||||
pke_csr.rmwf(utra::pke::SFR_CRFUNC_SFR_CRFUNC, bar);
|
||||
let mut baz = pke_csr.zf(utra::pke::SFR_CRFUNC_SFR_CRFUNC, bar);
|
||||
baz |= pke_csr.ms(utra::pke::SFR_CRFUNC_SFR_CRFUNC, 1);
|
||||
pke_csr.wfo(utra::pke::SFR_CRFUNC_SFR_CRFUNC, baz);
|
||||
let bar = pke_csr.rf(utra::pke::SFR_CRFUNC_CR_FUNC);
|
||||
pke_csr.rmwf(utra::pke::SFR_CRFUNC_CR_FUNC, bar);
|
||||
let mut baz = pke_csr.zf(utra::pke::SFR_CRFUNC_CR_FUNC, bar);
|
||||
baz |= pke_csr.ms(utra::pke::SFR_CRFUNC_CR_FUNC, 1);
|
||||
pke_csr.wfo(utra::pke::SFR_CRFUNC_CR_FUNC, baz);
|
||||
let bar = pke_csr.rf(utra::pke::SFR_CRFUNC_CR_PCOREIR);
|
||||
pke_csr.rmwf(utra::pke::SFR_CRFUNC_CR_PCOREIR, bar);
|
||||
let mut baz = pke_csr.zf(utra::pke::SFR_CRFUNC_CR_PCOREIR, bar);
|
||||
baz |= pke_csr.ms(utra::pke::SFR_CRFUNC_CR_PCOREIR, 1);
|
||||
pke_csr.wfo(utra::pke::SFR_CRFUNC_CR_PCOREIR, baz);
|
||||
|
||||
let foo = pke_csr.r(utra::pke::SFR_AR);
|
||||
pke_csr.wo(utra::pke::SFR_AR, foo);
|
||||
|
|
@ -15084,6 +15191,22 @@ mod tests {
|
|||
baz |= pke_csr.ms(utra::pke::SFR_OPTEW_SFR_OPTEW, 1);
|
||||
pke_csr.wfo(utra::pke::SFR_OPTEW_SFR_OPTEW, baz);
|
||||
|
||||
let foo = pke_csr.r(utra::pke::SFR_OPTRW);
|
||||
pke_csr.wo(utra::pke::SFR_OPTRW, foo);
|
||||
let bar = pke_csr.rf(utra::pke::SFR_OPTRW_SFR_OPTRW);
|
||||
pke_csr.rmwf(utra::pke::SFR_OPTRW_SFR_OPTRW, bar);
|
||||
let mut baz = pke_csr.zf(utra::pke::SFR_OPTRW_SFR_OPTRW, bar);
|
||||
baz |= pke_csr.ms(utra::pke::SFR_OPTRW_SFR_OPTRW, 1);
|
||||
pke_csr.wfo(utra::pke::SFR_OPTRW_SFR_OPTRW, baz);
|
||||
|
||||
let foo = pke_csr.r(utra::pke::SFR_OPTLTX);
|
||||
pke_csr.wo(utra::pke::SFR_OPTLTX, foo);
|
||||
let bar = pke_csr.rf(utra::pke::SFR_OPTLTX_SFR_OPTLTX);
|
||||
pke_csr.rmwf(utra::pke::SFR_OPTLTX_SFR_OPTLTX, bar);
|
||||
let mut baz = pke_csr.zf(utra::pke::SFR_OPTLTX_SFR_OPTLTX, bar);
|
||||
baz |= pke_csr.ms(utra::pke::SFR_OPTLTX_SFR_OPTLTX, 1);
|
||||
pke_csr.wfo(utra::pke::SFR_OPTLTX_SFR_OPTLTX, baz);
|
||||
|
||||
let foo = pke_csr.r(utra::pke::SFR_OPTMASK);
|
||||
pke_csr.wo(utra::pke::SFR_OPTMASK, foo);
|
||||
let bar = pke_csr.rf(utra::pke::SFR_OPTMASK_SFR_OPTMASK);
|
||||
|
|
@ -15346,13 +15469,13 @@ mod tests {
|
|||
baz |= sce_glbsfr_csr.ms(utra::sce_glbsfr::SFR_ARCLR_AR_CLRRAM, 1);
|
||||
sce_glbsfr_csr.wfo(utra::sce_glbsfr::SFR_ARCLR_AR_CLRRAM, baz);
|
||||
|
||||
let foo = sce_glbsfr_csr.r(utra::sce_glbsfr::SFR_TICKCYC);
|
||||
sce_glbsfr_csr.wo(utra::sce_glbsfr::SFR_TICKCYC, foo);
|
||||
let bar = sce_glbsfr_csr.rf(utra::sce_glbsfr::SFR_TICKCYC_SFR_TICKCYC);
|
||||
sce_glbsfr_csr.rmwf(utra::sce_glbsfr::SFR_TICKCYC_SFR_TICKCYC, bar);
|
||||
let mut baz = sce_glbsfr_csr.zf(utra::sce_glbsfr::SFR_TICKCYC_SFR_TICKCYC, bar);
|
||||
baz |= sce_glbsfr_csr.ms(utra::sce_glbsfr::SFR_TICKCYC_SFR_TICKCYC, 1);
|
||||
sce_glbsfr_csr.wfo(utra::sce_glbsfr::SFR_TICKCYC_SFR_TICKCYC, baz);
|
||||
let foo = sce_glbsfr_csr.r(utra::sce_glbsfr::SFR_FRACERR);
|
||||
sce_glbsfr_csr.wo(utra::sce_glbsfr::SFR_FRACERR, foo);
|
||||
let bar = sce_glbsfr_csr.rf(utra::sce_glbsfr::SFR_FRACERR_FR_ACERR);
|
||||
sce_glbsfr_csr.rmwf(utra::sce_glbsfr::SFR_FRACERR_FR_ACERR, bar);
|
||||
let mut baz = sce_glbsfr_csr.zf(utra::sce_glbsfr::SFR_FRACERR_FR_ACERR, bar);
|
||||
baz |= sce_glbsfr_csr.ms(utra::sce_glbsfr::SFR_FRACERR_FR_ACERR, 1);
|
||||
sce_glbsfr_csr.wfo(utra::sce_glbsfr::SFR_FRACERR_FR_ACERR, baz);
|
||||
|
||||
let foo = sce_glbsfr_csr.r(utra::sce_glbsfr::SFR_TICKCNT);
|
||||
sce_glbsfr_csr.wo(utra::sce_glbsfr::SFR_TICKCNT, foo);
|
||||
|
|
@ -15425,6 +15548,14 @@ mod tests {
|
|||
let mut baz = sce_glbsfr_csr.zf(utra::sce_glbsfr::SFR_FFCNT_SR_FF5_SR_FF5, bar);
|
||||
baz |= sce_glbsfr_csr.ms(utra::sce_glbsfr::SFR_FFCNT_SR_FF5_SR_FF5, 1);
|
||||
sce_glbsfr_csr.wfo(utra::sce_glbsfr::SFR_FFCNT_SR_FF5_SR_FF5, baz);
|
||||
|
||||
let foo = sce_glbsfr_csr.r(utra::sce_glbsfr::SFR_TS);
|
||||
sce_glbsfr_csr.wo(utra::sce_glbsfr::SFR_TS, foo);
|
||||
let bar = sce_glbsfr_csr.rf(utra::sce_glbsfr::SFR_TS_CR_TS);
|
||||
sce_glbsfr_csr.rmwf(utra::sce_glbsfr::SFR_TS_CR_TS, bar);
|
||||
let mut baz = sce_glbsfr_csr.zf(utra::sce_glbsfr::SFR_TS_CR_TS, bar);
|
||||
baz |= sce_glbsfr_csr.ms(utra::sce_glbsfr::SFR_TS_CR_TS, 1);
|
||||
sce_glbsfr_csr.wfo(utra::sce_glbsfr::SFR_TS_CR_TS, baz);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -15441,13 +15572,13 @@ mod tests {
|
|||
baz |= trng_csr.ms(utra::trng::SFR_CRSRC_SFR_CRSRC, 1);
|
||||
trng_csr.wfo(utra::trng::SFR_CRSRC_SFR_CRSRC, baz);
|
||||
|
||||
let foo = trng_csr.r(utra::trng::SFR_AR_STOP);
|
||||
trng_csr.wo(utra::trng::SFR_AR_STOP, foo);
|
||||
let bar = trng_csr.rf(utra::trng::SFR_AR_STOP_SFR_AR_STOP);
|
||||
trng_csr.rmwf(utra::trng::SFR_AR_STOP_SFR_AR_STOP, bar);
|
||||
let mut baz = trng_csr.zf(utra::trng::SFR_AR_STOP_SFR_AR_STOP, bar);
|
||||
baz |= trng_csr.ms(utra::trng::SFR_AR_STOP_SFR_AR_STOP, 1);
|
||||
trng_csr.wfo(utra::trng::SFR_AR_STOP_SFR_AR_STOP, baz);
|
||||
let foo = trng_csr.r(utra::trng::SFR_CRANA);
|
||||
trng_csr.wo(utra::trng::SFR_CRANA, foo);
|
||||
let bar = trng_csr.rf(utra::trng::SFR_CRANA_SFR_CRANA);
|
||||
trng_csr.rmwf(utra::trng::SFR_CRANA_SFR_CRANA, bar);
|
||||
let mut baz = trng_csr.zf(utra::trng::SFR_CRANA_SFR_CRANA, bar);
|
||||
baz |= trng_csr.ms(utra::trng::SFR_CRANA_SFR_CRANA, 1);
|
||||
trng_csr.wfo(utra::trng::SFR_CRANA_SFR_CRANA, baz);
|
||||
|
||||
let foo = trng_csr.r(utra::trng::SFR_PP);
|
||||
trng_csr.wo(utra::trng::SFR_PP, foo);
|
||||
|
|
@ -15472,6 +15603,38 @@ mod tests {
|
|||
let mut baz = trng_csr.zf(utra::trng::SFR_SR_SR_RNG, bar);
|
||||
baz |= trng_csr.ms(utra::trng::SFR_SR_SR_RNG, 1);
|
||||
trng_csr.wfo(utra::trng::SFR_SR_SR_RNG, baz);
|
||||
|
||||
let foo = trng_csr.r(utra::trng::SFR_AR_GEN);
|
||||
trng_csr.wo(utra::trng::SFR_AR_GEN, foo);
|
||||
let bar = trng_csr.rf(utra::trng::SFR_AR_GEN_SFR_AR_GEN);
|
||||
trng_csr.rmwf(utra::trng::SFR_AR_GEN_SFR_AR_GEN, bar);
|
||||
let mut baz = trng_csr.zf(utra::trng::SFR_AR_GEN_SFR_AR_GEN, bar);
|
||||
baz |= trng_csr.ms(utra::trng::SFR_AR_GEN_SFR_AR_GEN, 1);
|
||||
trng_csr.wfo(utra::trng::SFR_AR_GEN_SFR_AR_GEN, baz);
|
||||
|
||||
let foo = trng_csr.r(utra::trng::SFR_FR);
|
||||
trng_csr.wo(utra::trng::SFR_FR, foo);
|
||||
let bar = trng_csr.rf(utra::trng::SFR_FR_SFR_FR);
|
||||
trng_csr.rmwf(utra::trng::SFR_FR_SFR_FR, bar);
|
||||
let mut baz = trng_csr.zf(utra::trng::SFR_FR_SFR_FR, bar);
|
||||
baz |= trng_csr.ms(utra::trng::SFR_FR_SFR_FR, 1);
|
||||
trng_csr.wfo(utra::trng::SFR_FR_SFR_FR, baz);
|
||||
|
||||
let foo = trng_csr.r(utra::trng::SFR_CHAIN_RNGCHAINEN0);
|
||||
trng_csr.wo(utra::trng::SFR_CHAIN_RNGCHAINEN0, foo);
|
||||
let bar = trng_csr.rf(utra::trng::SFR_CHAIN_RNGCHAINEN0_RNGCHAINEN0);
|
||||
trng_csr.rmwf(utra::trng::SFR_CHAIN_RNGCHAINEN0_RNGCHAINEN0, bar);
|
||||
let mut baz = trng_csr.zf(utra::trng::SFR_CHAIN_RNGCHAINEN0_RNGCHAINEN0, bar);
|
||||
baz |= trng_csr.ms(utra::trng::SFR_CHAIN_RNGCHAINEN0_RNGCHAINEN0, 1);
|
||||
trng_csr.wfo(utra::trng::SFR_CHAIN_RNGCHAINEN0_RNGCHAINEN0, baz);
|
||||
|
||||
let foo = trng_csr.r(utra::trng::SFR_CHAIN_RNGCHAINEN1);
|
||||
trng_csr.wo(utra::trng::SFR_CHAIN_RNGCHAINEN1, foo);
|
||||
let bar = trng_csr.rf(utra::trng::SFR_CHAIN_RNGCHAINEN1_RNGCHAINEN1);
|
||||
trng_csr.rmwf(utra::trng::SFR_CHAIN_RNGCHAINEN1_RNGCHAINEN1, bar);
|
||||
let mut baz = trng_csr.zf(utra::trng::SFR_CHAIN_RNGCHAINEN1_RNGCHAINEN1, bar);
|
||||
baz |= trng_csr.ms(utra::trng::SFR_CHAIN_RNGCHAINEN1_RNGCHAINEN1, 1);
|
||||
trng_csr.wfo(utra::trng::SFR_CHAIN_RNGCHAINEN1_RNGCHAINEN1, baz);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -15747,45 +15910,53 @@ mod tests {
|
|||
baz |= sysctrl_csr.ms(utra::sysctrl::SFR_CGUSEL0_SFR_CGUSEL0, 1);
|
||||
sysctrl_csr.wfo(utra::sysctrl::SFR_CGUSEL0_SFR_CGUSEL0, baz);
|
||||
|
||||
let foo = sysctrl_csr.r(utra::sysctrl::SFR_CGUFD_CFGFDCR0);
|
||||
sysctrl_csr.wo(utra::sysctrl::SFR_CGUFD_CFGFDCR0, foo);
|
||||
let bar = sysctrl_csr.rf(utra::sysctrl::SFR_CGUFD_CFGFDCR0_CFGFDCR0);
|
||||
sysctrl_csr.rmwf(utra::sysctrl::SFR_CGUFD_CFGFDCR0_CFGFDCR0, bar);
|
||||
let mut baz = sysctrl_csr.zf(utra::sysctrl::SFR_CGUFD_CFGFDCR0_CFGFDCR0, bar);
|
||||
baz |= sysctrl_csr.ms(utra::sysctrl::SFR_CGUFD_CFGFDCR0_CFGFDCR0, 1);
|
||||
sysctrl_csr.wfo(utra::sysctrl::SFR_CGUFD_CFGFDCR0_CFGFDCR0, baz);
|
||||
let foo = sysctrl_csr.r(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_0);
|
||||
sysctrl_csr.wo(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_0, foo);
|
||||
let bar = sysctrl_csr.rf(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_0_CFGFDCR_0_4_0);
|
||||
sysctrl_csr.rmwf(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_0_CFGFDCR_0_4_0, bar);
|
||||
let mut baz = sysctrl_csr.zf(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_0_CFGFDCR_0_4_0, bar);
|
||||
baz |= sysctrl_csr.ms(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_0_CFGFDCR_0_4_0, 1);
|
||||
sysctrl_csr.wfo(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_0_CFGFDCR_0_4_0, baz);
|
||||
|
||||
let foo = sysctrl_csr.r(utra::sysctrl::SFR_CGUFD_CFGFDCR1);
|
||||
sysctrl_csr.wo(utra::sysctrl::SFR_CGUFD_CFGFDCR1, foo);
|
||||
let bar = sysctrl_csr.rf(utra::sysctrl::SFR_CGUFD_CFGFDCR1_CFGFDCR1);
|
||||
sysctrl_csr.rmwf(utra::sysctrl::SFR_CGUFD_CFGFDCR1_CFGFDCR1, bar);
|
||||
let mut baz = sysctrl_csr.zf(utra::sysctrl::SFR_CGUFD_CFGFDCR1_CFGFDCR1, bar);
|
||||
baz |= sysctrl_csr.ms(utra::sysctrl::SFR_CGUFD_CFGFDCR1_CFGFDCR1, 1);
|
||||
sysctrl_csr.wfo(utra::sysctrl::SFR_CGUFD_CFGFDCR1_CFGFDCR1, baz);
|
||||
let foo = sysctrl_csr.r(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_1);
|
||||
sysctrl_csr.wo(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_1, foo);
|
||||
let bar = sysctrl_csr.rf(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_1_CFGFDCR_0_4_1);
|
||||
sysctrl_csr.rmwf(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_1_CFGFDCR_0_4_1, bar);
|
||||
let mut baz = sysctrl_csr.zf(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_1_CFGFDCR_0_4_1, bar);
|
||||
baz |= sysctrl_csr.ms(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_1_CFGFDCR_0_4_1, 1);
|
||||
sysctrl_csr.wfo(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_1_CFGFDCR_0_4_1, baz);
|
||||
|
||||
let foo = sysctrl_csr.r(utra::sysctrl::SFR_CGUFD_CFGFDCR2);
|
||||
sysctrl_csr.wo(utra::sysctrl::SFR_CGUFD_CFGFDCR2, foo);
|
||||
let bar = sysctrl_csr.rf(utra::sysctrl::SFR_CGUFD_CFGFDCR2_CFGFDCR2);
|
||||
sysctrl_csr.rmwf(utra::sysctrl::SFR_CGUFD_CFGFDCR2_CFGFDCR2, bar);
|
||||
let mut baz = sysctrl_csr.zf(utra::sysctrl::SFR_CGUFD_CFGFDCR2_CFGFDCR2, bar);
|
||||
baz |= sysctrl_csr.ms(utra::sysctrl::SFR_CGUFD_CFGFDCR2_CFGFDCR2, 1);
|
||||
sysctrl_csr.wfo(utra::sysctrl::SFR_CGUFD_CFGFDCR2_CFGFDCR2, baz);
|
||||
let foo = sysctrl_csr.r(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_2);
|
||||
sysctrl_csr.wo(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_2, foo);
|
||||
let bar = sysctrl_csr.rf(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_2_CFGFDCR_0_4_2);
|
||||
sysctrl_csr.rmwf(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_2_CFGFDCR_0_4_2, bar);
|
||||
let mut baz = sysctrl_csr.zf(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_2_CFGFDCR_0_4_2, bar);
|
||||
baz |= sysctrl_csr.ms(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_2_CFGFDCR_0_4_2, 1);
|
||||
sysctrl_csr.wfo(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_2_CFGFDCR_0_4_2, baz);
|
||||
|
||||
let foo = sysctrl_csr.r(utra::sysctrl::SFR_CGUFD_CFGFDCR3);
|
||||
sysctrl_csr.wo(utra::sysctrl::SFR_CGUFD_CFGFDCR3, foo);
|
||||
let bar = sysctrl_csr.rf(utra::sysctrl::SFR_CGUFD_CFGFDCR3_CFGFDCR3);
|
||||
sysctrl_csr.rmwf(utra::sysctrl::SFR_CGUFD_CFGFDCR3_CFGFDCR3, bar);
|
||||
let mut baz = sysctrl_csr.zf(utra::sysctrl::SFR_CGUFD_CFGFDCR3_CFGFDCR3, bar);
|
||||
baz |= sysctrl_csr.ms(utra::sysctrl::SFR_CGUFD_CFGFDCR3_CFGFDCR3, 1);
|
||||
sysctrl_csr.wfo(utra::sysctrl::SFR_CGUFD_CFGFDCR3_CFGFDCR3, baz);
|
||||
let foo = sysctrl_csr.r(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_3);
|
||||
sysctrl_csr.wo(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_3, foo);
|
||||
let bar = sysctrl_csr.rf(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_3_CFGFDCR_0_4_3);
|
||||
sysctrl_csr.rmwf(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_3_CFGFDCR_0_4_3, bar);
|
||||
let mut baz = sysctrl_csr.zf(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_3_CFGFDCR_0_4_3, bar);
|
||||
baz |= sysctrl_csr.ms(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_3_CFGFDCR_0_4_3, 1);
|
||||
sysctrl_csr.wfo(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_3_CFGFDCR_0_4_3, baz);
|
||||
|
||||
let foo = sysctrl_csr.r(utra::sysctrl::SFR_CGUFD_CFGFDCR4);
|
||||
sysctrl_csr.wo(utra::sysctrl::SFR_CGUFD_CFGFDCR4, foo);
|
||||
let bar = sysctrl_csr.rf(utra::sysctrl::SFR_CGUFD_CFGFDCR4_CFGFDCR4);
|
||||
sysctrl_csr.rmwf(utra::sysctrl::SFR_CGUFD_CFGFDCR4_CFGFDCR4, bar);
|
||||
let mut baz = sysctrl_csr.zf(utra::sysctrl::SFR_CGUFD_CFGFDCR4_CFGFDCR4, bar);
|
||||
baz |= sysctrl_csr.ms(utra::sysctrl::SFR_CGUFD_CFGFDCR4_CFGFDCR4, 1);
|
||||
sysctrl_csr.wfo(utra::sysctrl::SFR_CGUFD_CFGFDCR4_CFGFDCR4, baz);
|
||||
let foo = sysctrl_csr.r(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_4);
|
||||
sysctrl_csr.wo(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_4, foo);
|
||||
let bar = sysctrl_csr.rf(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_4_CFGFDCR_0_4_4);
|
||||
sysctrl_csr.rmwf(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_4_CFGFDCR_0_4_4, bar);
|
||||
let mut baz = sysctrl_csr.zf(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_4_CFGFDCR_0_4_4, bar);
|
||||
baz |= sysctrl_csr.ms(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_4_CFGFDCR_0_4_4, 1);
|
||||
sysctrl_csr.wfo(utra::sysctrl::SFR_CGUFD_CFGFDCR_0_4_4_CFGFDCR_0_4_4, baz);
|
||||
|
||||
let foo = sysctrl_csr.r(utra::sysctrl::SFR_CGUFDAO);
|
||||
sysctrl_csr.wo(utra::sysctrl::SFR_CGUFDAO, foo);
|
||||
let bar = sysctrl_csr.rf(utra::sysctrl::SFR_CGUFDAO_CFGFDCR);
|
||||
sysctrl_csr.rmwf(utra::sysctrl::SFR_CGUFDAO_CFGFDCR, bar);
|
||||
let mut baz = sysctrl_csr.zf(utra::sysctrl::SFR_CGUFDAO_CFGFDCR, bar);
|
||||
baz |= sysctrl_csr.ms(utra::sysctrl::SFR_CGUFDAO_CFGFDCR, 1);
|
||||
sysctrl_csr.wfo(utra::sysctrl::SFR_CGUFDAO_CFGFDCR, baz);
|
||||
|
||||
let foo = sysctrl_csr.r(utra::sysctrl::SFR_CGUSET);
|
||||
sysctrl_csr.wo(utra::sysctrl::SFR_CGUSET, foo);
|
||||
|
|
@ -15803,6 +15974,14 @@ mod tests {
|
|||
baz |= sysctrl_csr.ms(utra::sysctrl::SFR_CGUSEL1_SFR_CGUSEL1, 1);
|
||||
sysctrl_csr.wfo(utra::sysctrl::SFR_CGUSEL1_SFR_CGUSEL1, baz);
|
||||
|
||||
let foo = sysctrl_csr.r(utra::sysctrl::SFR_CGUFDPKE);
|
||||
sysctrl_csr.wo(utra::sysctrl::SFR_CGUFDPKE, foo);
|
||||
let bar = sysctrl_csr.rf(utra::sysctrl::SFR_CGUFDPKE_SFR_CGUFDPKE);
|
||||
sysctrl_csr.rmwf(utra::sysctrl::SFR_CGUFDPKE_SFR_CGUFDPKE, bar);
|
||||
let mut baz = sysctrl_csr.zf(utra::sysctrl::SFR_CGUFDPKE_SFR_CGUFDPKE, bar);
|
||||
baz |= sysctrl_csr.ms(utra::sysctrl::SFR_CGUFDPKE_SFR_CGUFDPKE, 1);
|
||||
sysctrl_csr.wfo(utra::sysctrl::SFR_CGUFDPKE_SFR_CGUFDPKE, baz);
|
||||
|
||||
let foo = sysctrl_csr.r(utra::sysctrl::SFR_CGUFSSR_FSFREQ0);
|
||||
sysctrl_csr.wo(utra::sysctrl::SFR_CGUFSSR_FSFREQ0, foo);
|
||||
let bar = sysctrl_csr.rf(utra::sysctrl::SFR_CGUFSSR_FSFREQ0_FSFREQ0);
|
||||
|
|
@ -18808,6 +18987,61 @@ mod tests {
|
|||
rp_pio_csr.wfo(utra::rp_pio::SFR_ZERO3_SFR_ZERO3, baz);
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[ignore]
|
||||
fn compile_check_coresub_sramtrm_csr() {
|
||||
use super::*;
|
||||
let mut coresub_sramtrm_csr = CSR::new(HW_CORESUB_SRAMTRM_BASE as *mut u32);
|
||||
|
||||
let foo = coresub_sramtrm_csr.r(utra::coresub_sramtrm::SFR_CACHE);
|
||||
coresub_sramtrm_csr.wo(utra::coresub_sramtrm::SFR_CACHE, foo);
|
||||
let bar = coresub_sramtrm_csr.rf(utra::coresub_sramtrm::SFR_CACHE_SFR_CACHE);
|
||||
coresub_sramtrm_csr.rmwf(utra::coresub_sramtrm::SFR_CACHE_SFR_CACHE, bar);
|
||||
let mut baz = coresub_sramtrm_csr.zf(utra::coresub_sramtrm::SFR_CACHE_SFR_CACHE, bar);
|
||||
baz |= coresub_sramtrm_csr.ms(utra::coresub_sramtrm::SFR_CACHE_SFR_CACHE, 1);
|
||||
coresub_sramtrm_csr.wfo(utra::coresub_sramtrm::SFR_CACHE_SFR_CACHE, baz);
|
||||
|
||||
let foo = coresub_sramtrm_csr.r(utra::coresub_sramtrm::SFR_ITCM);
|
||||
coresub_sramtrm_csr.wo(utra::coresub_sramtrm::SFR_ITCM, foo);
|
||||
let bar = coresub_sramtrm_csr.rf(utra::coresub_sramtrm::SFR_ITCM_SFR_ITCM);
|
||||
coresub_sramtrm_csr.rmwf(utra::coresub_sramtrm::SFR_ITCM_SFR_ITCM, bar);
|
||||
let mut baz = coresub_sramtrm_csr.zf(utra::coresub_sramtrm::SFR_ITCM_SFR_ITCM, bar);
|
||||
baz |= coresub_sramtrm_csr.ms(utra::coresub_sramtrm::SFR_ITCM_SFR_ITCM, 1);
|
||||
coresub_sramtrm_csr.wfo(utra::coresub_sramtrm::SFR_ITCM_SFR_ITCM, baz);
|
||||
|
||||
let foo = coresub_sramtrm_csr.r(utra::coresub_sramtrm::SFR_DTCM);
|
||||
coresub_sramtrm_csr.wo(utra::coresub_sramtrm::SFR_DTCM, foo);
|
||||
let bar = coresub_sramtrm_csr.rf(utra::coresub_sramtrm::SFR_DTCM_SFR_DTCM);
|
||||
coresub_sramtrm_csr.rmwf(utra::coresub_sramtrm::SFR_DTCM_SFR_DTCM, bar);
|
||||
let mut baz = coresub_sramtrm_csr.zf(utra::coresub_sramtrm::SFR_DTCM_SFR_DTCM, bar);
|
||||
baz |= coresub_sramtrm_csr.ms(utra::coresub_sramtrm::SFR_DTCM_SFR_DTCM, 1);
|
||||
coresub_sramtrm_csr.wfo(utra::coresub_sramtrm::SFR_DTCM_SFR_DTCM, baz);
|
||||
|
||||
let foo = coresub_sramtrm_csr.r(utra::coresub_sramtrm::SFR_SRAM0);
|
||||
coresub_sramtrm_csr.wo(utra::coresub_sramtrm::SFR_SRAM0, foo);
|
||||
let bar = coresub_sramtrm_csr.rf(utra::coresub_sramtrm::SFR_SRAM0_SFR_SRAM0);
|
||||
coresub_sramtrm_csr.rmwf(utra::coresub_sramtrm::SFR_SRAM0_SFR_SRAM0, bar);
|
||||
let mut baz = coresub_sramtrm_csr.zf(utra::coresub_sramtrm::SFR_SRAM0_SFR_SRAM0, bar);
|
||||
baz |= coresub_sramtrm_csr.ms(utra::coresub_sramtrm::SFR_SRAM0_SFR_SRAM0, 1);
|
||||
coresub_sramtrm_csr.wfo(utra::coresub_sramtrm::SFR_SRAM0_SFR_SRAM0, baz);
|
||||
|
||||
let foo = coresub_sramtrm_csr.r(utra::coresub_sramtrm::SFR_SRAM1);
|
||||
coresub_sramtrm_csr.wo(utra::coresub_sramtrm::SFR_SRAM1, foo);
|
||||
let bar = coresub_sramtrm_csr.rf(utra::coresub_sramtrm::SFR_SRAM1_SFR_SRAM1);
|
||||
coresub_sramtrm_csr.rmwf(utra::coresub_sramtrm::SFR_SRAM1_SFR_SRAM1, bar);
|
||||
let mut baz = coresub_sramtrm_csr.zf(utra::coresub_sramtrm::SFR_SRAM1_SFR_SRAM1, bar);
|
||||
baz |= coresub_sramtrm_csr.ms(utra::coresub_sramtrm::SFR_SRAM1_SFR_SRAM1, 1);
|
||||
coresub_sramtrm_csr.wfo(utra::coresub_sramtrm::SFR_SRAM1_SFR_SRAM1, baz);
|
||||
|
||||
let foo = coresub_sramtrm_csr.r(utra::coresub_sramtrm::SFR_VEXRAM);
|
||||
coresub_sramtrm_csr.wo(utra::coresub_sramtrm::SFR_VEXRAM, foo);
|
||||
let bar = coresub_sramtrm_csr.rf(utra::coresub_sramtrm::SFR_VEXRAM_SFR_VEXRAM);
|
||||
coresub_sramtrm_csr.rmwf(utra::coresub_sramtrm::SFR_VEXRAM_SFR_VEXRAM, bar);
|
||||
let mut baz = coresub_sramtrm_csr.zf(utra::coresub_sramtrm::SFR_VEXRAM_SFR_VEXRAM, bar);
|
||||
baz |= coresub_sramtrm_csr.ms(utra::coresub_sramtrm::SFR_VEXRAM_SFR_VEXRAM, 1);
|
||||
coresub_sramtrm_csr.wfo(utra::coresub_sramtrm::SFR_VEXRAM_SFR_VEXRAM, baz);
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[ignore]
|
||||
fn compile_check_mdma_csr() {
|
||||
|
|
@ -19348,11 +19582,19 @@ mod tests {
|
|||
|
||||
let foo = sensorc_csr.r(utra::sensorc::SFR_VDSR);
|
||||
sensorc_csr.wo(utra::sensorc::SFR_VDSR, foo);
|
||||
let bar = sensorc_csr.rf(utra::sensorc::SFR_VDSR_SR_VDSR);
|
||||
sensorc_csr.rmwf(utra::sensorc::SFR_VDSR_SR_VDSR, bar);
|
||||
let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDSR_SR_VDSR, bar);
|
||||
baz |= sensorc_csr.ms(utra::sensorc::SFR_VDSR_SR_VDSR, 1);
|
||||
sensorc_csr.wfo(utra::sensorc::SFR_VDSR_SR_VDSR, baz);
|
||||
let bar = sensorc_csr.rf(utra::sensorc::SFR_VDSR_VDFLAG);
|
||||
sensorc_csr.rmwf(utra::sensorc::SFR_VDSR_VDFLAG, bar);
|
||||
let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDSR_VDFLAG, bar);
|
||||
baz |= sensorc_csr.ms(utra::sensorc::SFR_VDSR_VDFLAG, 1);
|
||||
sensorc_csr.wfo(utra::sensorc::SFR_VDSR_VDFLAG, baz);
|
||||
|
||||
let foo = sensorc_csr.r(utra::sensorc::SFR_VDFR);
|
||||
sensorc_csr.wo(utra::sensorc::SFR_VDFR, foo);
|
||||
let bar = sensorc_csr.rf(utra::sensorc::SFR_VDFR_VDFLAG);
|
||||
sensorc_csr.rmwf(utra::sensorc::SFR_VDFR_VDFLAG, bar);
|
||||
let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDFR_VDFLAG, bar);
|
||||
baz |= sensorc_csr.ms(utra::sensorc::SFR_VDFR_VDFLAG, 1);
|
||||
sensorc_csr.wfo(utra::sensorc::SFR_VDFR_VDFLAG, baz);
|
||||
|
||||
let foo = sensorc_csr.r(utra::sensorc::SFR_LDMASK);
|
||||
sensorc_csr.wo(utra::sensorc::SFR_LDMASK, foo);
|
||||
|
|
@ -19441,5 +19683,37 @@ mod tests {
|
|||
let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDCFG_CR_VDCFG7_CR_VDCFG7, bar);
|
||||
baz |= sensorc_csr.ms(utra::sensorc::SFR_VDCFG_CR_VDCFG7_CR_VDCFG7, 1);
|
||||
sensorc_csr.wfo(utra::sensorc::SFR_VDCFG_CR_VDCFG7_CR_VDCFG7, baz);
|
||||
|
||||
let foo = sensorc_csr.r(utra::sensorc::SFR_VDIP_ENA);
|
||||
sensorc_csr.wo(utra::sensorc::SFR_VDIP_ENA, foo);
|
||||
let bar = sensorc_csr.rf(utra::sensorc::SFR_VDIP_ENA_VDENA);
|
||||
sensorc_csr.rmwf(utra::sensorc::SFR_VDIP_ENA_VDENA, bar);
|
||||
let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDIP_ENA_VDENA, bar);
|
||||
baz |= sensorc_csr.ms(utra::sensorc::SFR_VDIP_ENA_VDENA, 1);
|
||||
sensorc_csr.wfo(utra::sensorc::SFR_VDIP_ENA_VDENA, baz);
|
||||
|
||||
let foo = sensorc_csr.r(utra::sensorc::SFR_VDIP_TEST);
|
||||
sensorc_csr.wo(utra::sensorc::SFR_VDIP_TEST, foo);
|
||||
let bar = sensorc_csr.rf(utra::sensorc::SFR_VDIP_TEST_VDTST);
|
||||
sensorc_csr.rmwf(utra::sensorc::SFR_VDIP_TEST_VDTST, bar);
|
||||
let mut baz = sensorc_csr.zf(utra::sensorc::SFR_VDIP_TEST_VDTST, bar);
|
||||
baz |= sensorc_csr.ms(utra::sensorc::SFR_VDIP_TEST_VDTST, 1);
|
||||
sensorc_csr.wfo(utra::sensorc::SFR_VDIP_TEST_VDTST, baz);
|
||||
|
||||
let foo = sensorc_csr.r(utra::sensorc::SFR_LDIP_TEST);
|
||||
sensorc_csr.wo(utra::sensorc::SFR_LDIP_TEST, foo);
|
||||
let bar = sensorc_csr.rf(utra::sensorc::SFR_LDIP_TEST_LDTST);
|
||||
sensorc_csr.rmwf(utra::sensorc::SFR_LDIP_TEST_LDTST, bar);
|
||||
let mut baz = sensorc_csr.zf(utra::sensorc::SFR_LDIP_TEST_LDTST, bar);
|
||||
baz |= sensorc_csr.ms(utra::sensorc::SFR_LDIP_TEST_LDTST, 1);
|
||||
sensorc_csr.wfo(utra::sensorc::SFR_LDIP_TEST_LDTST, baz);
|
||||
|
||||
let foo = sensorc_csr.r(utra::sensorc::SFR_LDIP_FD);
|
||||
sensorc_csr.wo(utra::sensorc::SFR_LDIP_FD, foo);
|
||||
let bar = sensorc_csr.rf(utra::sensorc::SFR_LDIP_FD_SFR_LDIP_FD);
|
||||
sensorc_csr.rmwf(utra::sensorc::SFR_LDIP_FD_SFR_LDIP_FD, bar);
|
||||
let mut baz = sensorc_csr.zf(utra::sensorc::SFR_LDIP_FD_SFR_LDIP_FD, bar);
|
||||
baz |= sensorc_csr.ms(utra::sensorc::SFR_LDIP_FD_SFR_LDIP_FD, 1);
|
||||
sensorc_csr.wfo(utra::sensorc::SFR_LDIP_FD_SFR_LDIP_FD, baz);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue