mirror of
https://github.com/saymrwulf/xous-core.git
synced 2026-11-04 04:27:34 +00:00
modify loader to setup the console UART
this avoids a bunch of nasty pinmux stuff that would have to go into the console logger at early boot
This commit is contained in:
parent
5116d51de5
commit
e2ba706f4b
1 changed files with 37 additions and 0 deletions
|
|
@ -124,4 +124,41 @@ pub fn early_init() {
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
use utralib::generated::*;
|
||||
|
||||
// configure the UDMA UART and send a test string. This UART's settings will be
|
||||
// used as the initial console UART.
|
||||
let mut udma_ctrl = CSR::new(utra::udma_ctrl::HW_UDMA_CTRL_BASE as *mut u32);
|
||||
let iox_csr = utra::iox::HW_IOX_BASE as *mut u32;
|
||||
unsafe {
|
||||
iox_csr.add(0).write_volatile(0b00_00_00_01_01_00_00_00); // PAL AF1 on PA3/PA4
|
||||
iox_csr.add(0x1c / core::mem::size_of::<u32>()).write_volatile(0x1400); // PDH
|
||||
iox_csr.add(0x148 / core::mem::size_of::<u32>()).write_volatile(0x10); // PA4 output
|
||||
iox_csr.add(0x148 / core::mem::size_of::<u32>() + 3).write_volatile(0xffff); // PD
|
||||
iox_csr.add(0x160 / core::mem::size_of::<u32>()).write_volatile(0x8); // PA3 pullup
|
||||
}
|
||||
udma_ctrl.wo(utra::udma_ctrl::REG_CG, 1);
|
||||
|
||||
let baudrate: u32 = 115200;
|
||||
let freq: u32 = 100_000_000;
|
||||
let clk_counter: u32 = (freq + baudrate / 2) / baudrate;
|
||||
let mut udma_uart = CSR::new(utra::udma_uart_0::HW_UDMA_UART_0_BASE as *mut u32);
|
||||
udma_uart.wo(utra::udma_uart_0::REG_UART_SETUP,
|
||||
0x0306 | (clk_counter << 16));
|
||||
|
||||
/*
|
||||
// send a test string to confirm the UART is configured
|
||||
let tx_buf = utralib::HW_IFRAM0_MEM as *mut u8;
|
||||
for i in 0..16 {
|
||||
unsafe { tx_buf.add(i).write_volatile('a' as u32 as u8 + i as u8) };
|
||||
}
|
||||
udma_uart.wo(utra::udma_uart_0::REG_TX_SADDR, tx_buf as u32);
|
||||
udma_uart.wo(utra::udma_uart_0::REG_TX_SIZE, 16);
|
||||
// send it
|
||||
udma_uart.wo(utra::udma_uart_0::REG_TX_CFG, 0x10); // EN
|
||||
// wait for it all to be done
|
||||
while udma_uart.rf(utra::udma_uart_0::REG_TX_CFG_R_TX_EN) != 0 { }
|
||||
while (udma_uart.r(utra::udma_uart_0::REG_STATUS) & 1) != 0 { }
|
||||
*/
|
||||
}
|
||||
Loading…
Reference in a new issue