From dff4dded64c7e632d2dca79149ef9e4e96f3d321 Mon Sep 17 00:00:00 2001
From: bunnie <bunnie@kosagi.com>
Date: Sun, 18 May 2025 04:25:37 +0800
Subject: [PATCH] remove yield_slice() in std target

This is a bad idea because yield_slice() causes the active
process to hand off to a new one (without an IRQ). However,
the idea of most flash operations is we really want them
atomic - we can't have something else decide to go and muck
with flash while say, we are waiting for a page erase to
complete. So, implement spin locking to block the CPU
during phases where the hardware operation is non-interruptable.
---
 libs/cramium-hal/src/udma/spim.rs | 40 +++++++++++++++----------------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/libs/cramium-hal/src/udma/spim.rs b/libs/cramium-hal/src/udma/spim.rs
index ff53ef0be..418514a46 100644
--- a/libs/cramium-hal/src/udma/spim.rs
+++ b/libs/cramium-hal/src/udma/spim.rs
@@ -584,8 +584,8 @@ impl Spim {
             // last iteration falls through without waiting...
             if words_sent < total_words {
                 while self.udma_busy(Bank::Tx) {
-                    #[cfg(feature = "std")]
-                    xous::yield_slice();
+                    // #[cfg(feature = "std")]
+                    // xous::yield_slice();
                 }
             }
         }
@@ -842,8 +842,8 @@ impl Spim {
         let cmd_list = [SpimCmd::SendCmd(self.mode, 8, cmd as u16)];
         self.send_cmd_list(&cmd_list);
         while self.udma_busy(Bank::Custom) {
-            #[cfg(feature = "std")]
-            xous::yield_slice();
+            // #[cfg(feature = "std")]
+            // xous::yield_slice();
         }
     }
 
@@ -868,8 +868,8 @@ impl Spim {
         };
         self.send_cmd_list(&cmd_list);
         while self.udma_busy(Bank::Rx) {
-            #[cfg(feature = "std")]
-            xous::yield_slice();
+            // #[cfg(feature = "std")]
+            // xous::yield_slice();
         }
 
         let ret = u32::from_le_bytes([self.rx_buf()[0], self.rx_buf()[1], self.rx_buf()[2], 0x0]);
@@ -899,8 +899,8 @@ impl Spim {
         };
         self.send_cmd_list(&cmd_list);
         while self.udma_busy(Bank::Rx) {
-            #[cfg(feature = "std")]
-            xous::yield_slice();
+            // #[cfg(feature = "std")]
+            // xous::yield_slice();
         }
 
         let ret =
@@ -947,8 +947,8 @@ impl Spim {
         self.send_cmd_list(&cmd_list);
 
         while self.udma_busy(Bank::Tx) {
-            #[cfg(feature = "std")]
-            xous::yield_slice();
+            // #[cfg(feature = "std")]
+            // xous::yield_slice();
         }
         self.mem_cs(false);
     }
@@ -1140,8 +1140,8 @@ impl Spim {
         };
         self.send_cmd_list(&cmd_list);
         while self.udma_busy(Bank::Rx) {
-            #[cfg(feature = "std")]
-            xous::yield_slice();
+            // #[cfg(feature = "std")]
+            // xous::yield_slice();
         }
         let ret = self.rx_buf()[0];
 
@@ -1163,8 +1163,8 @@ impl Spim {
         };
         self.send_cmd_list(&cmd_list);
         while self.udma_busy(Bank::Rx) {
-            #[cfg(feature = "std")]
-            xous::yield_slice();
+            // #[cfg(feature = "std")]
+            // xous::yield_slice();
         }
         let ret = self.rx_buf()[0];
 
@@ -1183,8 +1183,8 @@ impl Spim {
         self.send_cmd_list(&cmd_list);
 
         while self.udma_busy(Bank::Tx) {
-            #[cfg(feature = "std")]
-            xous::yield_slice();
+            // #[cfg(feature = "std")]
+            // xous::yield_slice();
         }
         self.mem_cs(false);
     }
@@ -1237,8 +1237,8 @@ impl Spim {
         self.send_cmd_list(&cmd_list);
 
         while self.udma_busy(Bank::Tx) {
-            #[cfg(feature = "std")]
-            xous::yield_slice();
+            // #[cfg(feature = "std")]
+            // xous::yield_slice();
         }
         self.mem_cs(false);
     }
@@ -1321,8 +1321,8 @@ impl Spim {
         self.send_cmd_list(&cmd_list);
 
         while self.udma_busy(Bank::Tx) {
-            #[cfg(feature = "std")]
-            xous::yield_slice();
+            // #[cfg(feature = "std")]
+            // xous::yield_slice();
         }
         self.mem_cs(false);