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https://github.com/saymrwulf/xous-core.git
synced 2026-11-15 08:30:02 +00:00
fix kernel debug input
for whatever reason, by default, uarts in litex are configured not to drain a fifo when you read them -- they only drain after you write EV_PENDING.
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parent
b6039361cf
commit
d42658a65d
1 changed files with 9 additions and 5 deletions
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@ -102,12 +102,16 @@ impl Uart {
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if unsafe { DEBUG_OUTPUT.is_none() } {
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return None;
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}
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let uart_csr = CSR::new(crate::debug::SUPERVISOR_UART_ADDR as *mut u32);
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let mut uart_csr = CSR::new(crate::debug::SUPERVISOR_UART_ADDR as *mut u32);
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// If EV_PENDING_RX is 1, return the pending character.
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// Otherwise, return None.
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match uart_csr.rf(utra::uart::RXEMPTY_RXEMPTY) {
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1 => None,
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_ => Some(uart_csr.r(utra::uart::RXTX) as u8),
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match uart_csr.rf(utra::uart::EV_PENDING_RX) {
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0 => None,
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_ => {
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let ret = Some(uart_csr.r(utra::uart::RXTX) as u8);
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uart_csr.wfo(utra::uart::EV_PENDING_RX, 1);
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ret
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},
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}
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}
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@ -157,7 +161,7 @@ pub fn irq(_irq_number: usize, _arg: *mut usize) {
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while let Some(b) = uart.getc() {
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process_irq_character(b);
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}
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uart.acknowledge_irq();
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// uart.acknowledge_irq();
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}
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fn process_irq_character(b: u8) {
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