mirror of
https://github.com/saymrwulf/xous-core.git
synced 2026-11-15 08:30:02 +00:00
add rtc hardware drivers and service
This commit is contained in:
bunnie
parent
cd8a312b8d
commit
d30d889774
3 changed files with 330 additions and 0 deletions
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@ -39,6 +39,8 @@ pub mod mbox;
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#[cfg(not(feature = "hosted-baosec"))]
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pub mod rram;
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// no signature checking in the kernel
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#[cfg(not(feature = "hosted-baosec"))]
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pub mod rtc;
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#[cfg(all(not(feature = "hosted-baosec"), not(feature = "kernel"),))]
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pub mod sigcheck;
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#[cfg(not(feature = "hosted-baosec"))]
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146
libs/bao1x-hal/src/rtc.rs
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146
libs/bao1x-hal/src/rtc.rs
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@ -0,0 +1,146 @@
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use utralib::*;
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/*
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The RTC is a weird bit of IP. It's a proprietary ARM block called the "PL031".
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Because we don't have the source code for it, we couldn't extract a standard UTRA
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header for the block. However, apparently ~ChatGPT~ knows about it, so I was able
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to ask it to help generate the following user guide.
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Query: "give me a C header file for the PL031 RTC block".
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Here is a concise C header for the ARM PrimeCell PL031 RTC block. Field offsets follow the ARM TRM. Adjust types or volatile rules as needed for your environment.
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#ifndef PL031_H
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#define PL031_H
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#include <stdint.h>
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#define PL031_BASE <insert location>
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/* Register offsets */
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#define PL031_DR 0x00 /* Data register */
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#define PL031_MR 0x04 /* Match register */
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#define PL031_LR 0x08 /* Load register */
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#define PL031_CR 0x0C /* Control register */
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#define PL031_IMSC 0x10 /* Interrupt mask set/clear */
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#define PL031_RIS 0x14 /* Raw interrupt status */
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#define PL031_MIS 0x18 /* Masked interrupt status */
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#define PL031_ICR 0x1C /* Interrupt clear */
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#define PL031_PERIPH_ID 0xFE0
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#define PL031_PCELL_ID 0xFF0
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/* Bit definitions */
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#define PL031_CR_EN (1U << 0)
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#define PL031_IMSC_MIS (1U << 0)
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#define PL031_RIS_RIS (1U << 0)
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#define PL031_MIS_MIS (1U << 0)
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#define PL031_ICR_CLR (1U << 0)
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/* Access helpers */
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static inline void pl031_write(uint32_t offset, uint32_t val) {
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*(volatile uint32_t *)(PL031_BASE + offset) = val;
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}
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static inline uint32_t pl031_read(uint32_t offset) {
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return *(volatile uint32_t *)(PL031_BASE + offset);
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}
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#endif
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LR (Load register, 0x08)
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Used to set the starting epoch. On the next second boundary, LR is copied into DR and becomes the running counter.
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MR (Match register, 0x04)
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Stores a compare value. When DR equals MR, the block asserts its interrupt. Software typically uses this for scheduled wakeups or periodic tasks.
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CR (Control register, 0x0C)
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Bit 0 enables or disables the RTC. When disabled, the counter stops incrementing.
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IMSC (Interrupt mask set or clear, 0x10)
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Controls whether the match event generates an interrupt to the CPU. Bit 0 is the mask.
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RIS (Raw interrupt status, 0x14)
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Reflects the unmasked interrupt state. Set when DR equals MR.
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MIS (Masked interrupt status, 0x18)
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Reflects the final interrupt state after masking. This is what software normally checks.
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ICR (Interrupt clear, 0x1C)
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Write 1 to bit 0 to clear the match interrupt so the next event can fire.
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Query: "how would i actually use this to keep time"
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To use the PL031 to keep time, treat it as a free running 1 Hz counter. The hardware increments the DR register once per second. The workflow has three steps.
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1. Initialize the counter
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Write an initial epoch value to LR, then enable the block.
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/* Set initial epoch time, for example UNIX time */
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pl031_write(PL031_LR, initial_epoch_seconds);
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/* Enable RTC */
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pl031_write(PL031_CR, PL031_CR_EN);
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The PL031 copies LR into DR on the next tick, then DR increments once every second.
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2. Read the current time
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Just read DR whenever you need seconds since the epoch you chose.
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uint32_t now = pl031_read(PL031_DR);
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If you want a fuller timestamp, convert now to a struct tm equivalent in software.
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3. Generate periodic events
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If your system needs periodic wakeups or scheduling:
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uint32_t t = pl031_read(PL031_DR);
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pl031_write(PL031_MR, t + interval_seconds);
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pl031_write(PL031_IMSC, PL031_IMSC_MIS); /* unmask interrupt */
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On interrupt, clear it and program the next match.
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pl031_write(PL031_ICR, PL031_ICR_CLR);
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Considerations
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If your system sleeps, the PL031 keeps running as long as its clock domain stays powered.
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If resets occur, reinitialize LR and CR.
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If subsecond precision is required, this peripheral cannot supply it; layer a software counter from a higher frequency timer.
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~Good enough for me!~
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*/
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// data register
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pub const DR: Register = Register::new(0, 0xFFFF_FFFF);
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// match register
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pub const MR: Register = Register::new(1, 0xFFFF_FFFF);
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// load register
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pub const LR: Register = Register::new(2, 0xFFFF_FFFF);
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// control register
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pub const CR: Register = Register::new(3, 1);
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pub const CR_EN: Field = Field::new(1, 0, CR);
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// interrupt mask set/clear
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pub const IMSC: Register = Register::new(4, 1);
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pub const IMSC_MASK: Field = Field::new(1, 0, IMSC);
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// raw interrupt status
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pub const RIS: Register = Register::new(5, 1);
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pub const RIS_STATUS: Field = Field::new(1, 0, RIS);
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// masked interrupt status
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pub const MIS: Register = Register::new(6, 1);
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pub const MIS_STATUS: Field = Field::new(1, 0, MIS);
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// interrupt clear
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pub const ICR: Register = Register::new(7, 1);
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pub const ICR_CLEAR: Field = Field::new(1, 0, ICR);
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// IP ID registers
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pub const PERI_ID: Register = Register::new(1016, 0xffff_ffff);
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pub const PRIME_ID: Register = Register::new(1020, 0xffff_ffff);
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pub const HW_RTC_BASE: usize = 0x40061000;
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pub const RTC_NUMREGS: usize = 10;
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182
services/bao1x-hal-service/src/servers/rtc.rs
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182
services/bao1x-hal-service/src/servers/rtc.rs
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@ -0,0 +1,182 @@
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use bao1x_hal::rtc::*;
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use utralib::*;
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use crate::api::TimeOp;
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/// This is a "well known name" used by `libstd` to connect to the time server
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/// Anyone who wants to check if time has been initialized would use this name.
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pub const TIME_SERVER_PUBLIC: &'static [u8; 16] = b"timeserverpublic";
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pub fn start_rtc_service() {
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let _ = std::thread::spawn({
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move || {
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rtc_service();
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}
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});
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}
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fn rtc_service() -> ! {
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// the public SID is well known and accessible by anyone who uses `libstd`
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let pub_sid =
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xous::create_server_with_address(&TIME_SERVER_PUBLIC).expect("Couldn't create Ticktimer server");
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let tt = ticktimer::Ticktimer::new().unwrap();
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let rtc_range = xous::map_memory(
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xous::MemoryAddress::new(bao1x_hal::rtc::HW_RTC_BASE),
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None,
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4096,
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xous::MemoryFlags::R | xous::MemoryFlags::W,
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)
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.expect("couldn't map RTC range");
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let rtc = CSR::new(rtc_range.as_mut_ptr() as *mut u32);
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// this loop allows us to fail slightly more gracefully in the case that there is an RTC hardware
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// failure
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let mut start_rtc_secs = rtc.r(DR);
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let mut start_tt_ms = tt.elapsed_ms();
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let mut utc_offset_ms = 0;
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let mut tz_offset_ms = 0;
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let mut msg_opt = None;
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let mut return_type = 0;
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loop {
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xous::reply_and_receive_next_legacy(pub_sid, &mut msg_opt, &mut return_type).unwrap();
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let msg = msg_opt.as_mut().unwrap();
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let opcode: Option<TimeOp> = num_traits::FromPrimitive::from_usize(msg.body.id());
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log::debug!("{:?}", opcode);
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match opcode {
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Some(TimeOp::HwSync) => {
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start_rtc_secs = rtc.r(DR);
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start_tt_ms = tt.elapsed_ms();
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}
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Some(TimeOp::GetUtcTimeMs) => {
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if let Some(scalar) = msg.body.scalar_message_mut() {
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let t = start_rtc_secs as i64 * 1000i64
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+ (tt.elapsed_ms() - start_tt_ms) as i64
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+ utc_offset_ms;
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if t < 0 {
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// the offset has some error in it, perhaps due to an RTC reset. reset the offset!
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log::warn!(
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"Time was negative, recovering from time setting error by clearing utc offset to 0"
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);
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utc_offset_ms = 0;
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}
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log::trace!("utc ms {}", t);
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// `Scalar2` return type
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return_type = 2;
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scalar.arg1 = (t as u64 & 0xFFFF_FFFF) as usize;
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scalar.arg2 = (((t as u64) >> 32) & 0xFFFF_FFFF) as usize;
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}
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}
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Some(TimeOp::GetLocalTimeMs) => {
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if let Some(scalar) = msg.body.scalar_message_mut() {
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log::trace!(
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"current offset {}",
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(start_rtc_secs as i64 * 1000i64 + (tt.elapsed_ms() - start_tt_ms) as i64) / 1000
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);
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let t = start_rtc_secs as i64 * 1000i64
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+ (tt.elapsed_ms() - start_tt_ms) as i64
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+ utc_offset_ms
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+ tz_offset_ms;
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if t < 0 {
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log::warn!(
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"Time was negative, recovering from time setting error by clearing utc and timezone offsets to 0."
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);
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utc_offset_ms = 0;
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tz_offset_ms = 0;
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}
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log::trace!("local since epoch {}", t / 1000);
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return_type = 2;
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scalar.arg1 = (((t as u64) >> 32) & 0xFFFF_FFFF) as usize;
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scalar.arg2 = (t as u64 & 0xFFFF_FFFF) as usize;
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}
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}
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/*
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Set with:
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log::info!("Got NTP time: {}.{}", time.sec(), time.sec_fraction());
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let current_time = Utc.with_ymd_and_hms(1970, 1, 1, 0, 0, 0).unwrap()
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+ chrono::Duration::seconds(time.sec() as i64);
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xous::send_message(
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timeserver_cid,
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Message::new_scalar(
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crate::time::TimeOp::SetUtcTimeMs.to_usize().unwrap(),
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((current_time.timestamp_millis() as u64) >> 32) as usize,
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(current_time.timestamp_millis() as u64 & 0xFFFF_FFFF) as usize,
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0,
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0,
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),
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)
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.expect("couldn't set time");
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*/
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Some(TimeOp::SetUtcTimeMs) => {
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if let Some(scalar) = msg.body.scalar_message() {
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let utc_hi_ms = scalar.arg1;
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let utc_lo_ms = scalar.arg2;
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let utc_time_ms = (utc_hi_ms as i64) << 32 | (utc_lo_ms as i64);
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start_rtc_secs = rtc.r(DR);
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start_tt_ms = tt.elapsed_ms();
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log::info!("utc_time: {}", utc_time_ms / 1000);
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log::info!("rtc_secs: {}", start_rtc_secs);
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log::info!("start_tt_ms: {}", start_tt_ms);
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let offset = utc_time_ms - (start_rtc_secs as i64) * 1000;
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utc_offset_ms = offset;
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}
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}
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/*
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`tz` is a float that represents the current UTC time offset (e.g. -8 for singapore)
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see simple_kilofloat_parse() in dns/src/time.rs for an efficient string parser if needed
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let tz_offset_ms = (tz * 3600) as i64;
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xous::send_message(
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timeserver_cid,
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Message::new_scalar(
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crate::time::TimeOp::SetTzOffsetMs.to_usize().unwrap(),
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(tz_offset_ms >> 32) as usize,
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(tz_offset_ms & 0xFFFF_FFFF) as usize,
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0,
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0,
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),
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)
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.expect("couldn't set timezone");
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*/
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Some(TimeOp::SetTzOffsetMs) => {
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if let Some(scalar) = msg.body.scalar_message() {
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let tz_hi_ms = scalar.arg1;
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let tz_lo_ms = scalar.arg2;
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let tz_ms = ((tz_hi_ms as i64) << 32) | (tz_lo_ms as i64);
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// sanity check with very broad bounds: I don't know of any time zones that are more
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// than +/2 days from UTC 86400 seconds in a day, times 1000
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// milliseconds, times 2 days
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if tz_ms < -(86400 * 1000 * 2) || tz_ms > 86400 * 1000 * 2 {
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log::warn!("Requested timezone offset {} is out of bounds, ignoring!", tz_ms);
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continue;
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} else {
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tz_offset_ms = tz_ms;
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}
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}
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}
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Some(TimeOp::WallClockTimeInit) => {
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if let Some(scalar) = msg.body.scalar_message_mut() {
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return_type = 2;
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if utc_offset_ms == 0 {
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scalar.arg1 = 0;
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} else {
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scalar.arg2 = 1;
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}
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}
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}
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// Calling this allows the caller to store the offsets used to compute the current
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// time from the RTC clock setting. The caller would restore time through a pair
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// of calls to SetUtcTimeMs with arg1/arg2, and SetTzOffsetMs with arg3/arg4.
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Some(TimeOp::GetState) => {
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if let Some(scalar) = msg.body.scalar_message_mut() {
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scalar.arg1 = (utc_offset_ms & 0xFFFF_FFFFF) as usize;
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scalar.arg2 = ((utc_offset_ms >> 32) & 0xFFFF_FFFF) as usize;
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scalar.arg3 = (tz_offset_ms & 0xFFFF_FFFF) as usize;
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scalar.arg4 = ((tz_offset_ms >> 32) & 0xFFFF_FFFF) as usize;
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}
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}
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None => log::error!("Time server public thread received unknown opcode: {:?}", msg),
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}
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}
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}
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