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https://github.com/saymrwulf/xous-core.git
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add axp2101 driver skeleton
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bunnie
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1 changed files with 308 additions and 0 deletions
308
libs/cramium-hal/src/axp2101.rs
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308
libs/cramium-hal/src/axp2101.rs
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use crate::udma::i2c;
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pub const AXP2101_DEV: u8 = 0x34;
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const REG_DCDC_ENA: usize = 0x80;
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const REG_DCDC1_V: usize = 0x82;
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const REG_DCDC2_V: usize = 0x83;
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const REG_DCDC3_V: usize = 0x84;
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const REG_DCDC4_V: usize = 0x85;
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#[allow(dead_code)]
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const REG_DCDC5_V: usize = 0x86;
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const REG_LDO1_ENA: usize = 0x90;
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const REG_LDO2_ENA: usize = 0x91;
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#[allow(dead_code)]
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const REG_ALDO1_V: usize = 0x92;
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#[allow(dead_code)]
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const REG_ALDO2_V: usize = 0x93;
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#[allow(dead_code)]
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const REG_ALDO3_V: usize = 0x94;
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#[allow(dead_code)]
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const REG_ALDO4_V: usize = 0x95;
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#[allow(dead_code)]
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const REG_BLDO1_V: usize = 0x96;
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#[allow(dead_code)]
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const REG_BLDO2_V: usize = 0x97;
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#[allow(dead_code)]
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const REG_CPUSLDO_V: usize = 0x98;
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#[allow(dead_code)]
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const REG_DLDO1_V: usize = 0x99;
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#[allow(dead_code)]
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const REG_DLDO2_V: usize = 0x9A;
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#[repr(u8)]
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#[derive(PartialEq, Eq, Clone, Copy)]
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pub enum WhichLdo {
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Aldo1 = 0,
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Aldo2 = 1,
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Aldo3 = 2,
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Aldo4 = 3,
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Bldo1 = 4,
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Bldo2 = 5,
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Cpusldo1 = 6,
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Dldo1 = 7,
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Dldo2 = 8,
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}
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impl Into<f32> for WhichLdo {
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fn into(self) -> f32 {
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match self {
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Self::Cpusldo1 | Self::Dldo1 => 0.050,
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_ => 0.100,
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}
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}
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}
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impl From<usize> for WhichLdo {
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fn from(value: usize) -> Self {
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match value {
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0 => Self::Aldo1,
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1 => Self::Aldo2,
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2 => Self::Aldo3,
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3 => Self::Aldo4,
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4 => Self::Bldo1,
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5 => Self::Bldo2,
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6 => Self::Cpusldo1,
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7 => Self::Dldo1,
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8 => Self::Dldo2,
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_ => panic!("bad WhichLdo"),
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}
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}
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}
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#[repr(usize)]
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#[derive(PartialEq, Eq, Copy, Clone)]
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pub enum WhichDcDc {
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Dcdc1 = 0,
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Dcdc2 = 1,
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Dcdc3 = 2,
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Dcdc4 = 3,
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Dcdc5 = 4,
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}
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impl From<usize> for WhichDcDc {
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fn from(value: usize) -> Self {
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match value {
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0 => Self::Dcdc1,
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1 => Self::Dcdc2,
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2 => Self::Dcdc3,
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3 => Self::Dcdc4,
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4 => Self::Dcdc5,
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_ => panic!("bad WhichDcDc"),
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}
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}
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}
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#[derive(Debug)]
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pub struct Axp2101 {
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pub dcdc_ena: [bool; 4],
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pub fast_ramp: bool,
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pub force_ccm: bool,
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pub dcdc_v_dvm: [(f32, bool); 4],
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pub ldo_ena: [bool; 9],
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pub ldo_v: [f32; 9],
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}
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impl Axp2101 {
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pub fn new(i2c: &mut dyn i2c::I2cApi) -> Axp2101 {
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let mut s = Axp2101 {
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dcdc_ena: [false; 4],
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fast_ramp: false,
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force_ccm: false,
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dcdc_v_dvm: [(0.0, false); 4],
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ldo_ena: [false; 9],
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ldo_v: [0.0; 9],
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};
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s.update(i2c);
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s
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}
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pub fn update(&mut self, i2c: &mut dyn i2c::I2cApi) {
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let mut buf = [0u8; 0xb0];
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i2c.i2c_read(AXP2101_DEV, 0x0, &mut buf, false).expect("couldn't access AXP2101");
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(self.dcdc_ena, self.fast_ramp, self.force_ccm) = parse_dcdc_ena(buf[REG_DCDC_ENA]);
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self.dcdc_v_dvm = [
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parse_dcdc(buf[REG_DCDC1_V], WhichDcDc::Dcdc1),
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parse_dcdc(buf[REG_DCDC2_V], WhichDcDc::Dcdc2),
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parse_dcdc(buf[REG_DCDC3_V], WhichDcDc::Dcdc3),
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parse_dcdc(buf[REG_DCDC4_V], WhichDcDc::Dcdc4),
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];
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for (i, ena) in self.ldo_ena.iter_mut().enumerate() {
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if i < 8 {
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*ena = (buf[REG_LDO1_ENA] >> i) & 1 != 0;
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} else {
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*ena = (buf[REG_LDO2_ENA] & 1) != 0;
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}
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}
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for (i, v) in self.ldo_v.iter_mut().enumerate() {
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*v = parse_ldo(buf[REG_ALDO1_V + i], WhichLdo::from(i));
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}
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}
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pub fn set_dcdc(
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&mut self,
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i2c: &mut dyn i2c::I2cApi,
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setting: Option<(f32, bool)>,
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which: WhichDcDc,
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) -> Result<(), xous::Error> {
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if let Some((voltage, dvm)) = setting {
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match encode_dcdc(voltage, dvm, which) {
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Some(code) => {
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self.dcdc_v_dvm[which as usize] = (voltage, dvm);
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self.dcdc_ena[which as usize] = true;
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i2c.i2c_write(AXP2101_DEV, (REG_DCDC1_V + which as usize) as u8, &[code]).map(|_| ())?;
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i2c.i2c_write(AXP2101_DEV, REG_DCDC_ENA as u8, &[self.encode_dcdc_ena()]).map(|_| ())
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}
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None => Err(xous::Error::InvalidLimit),
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}
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} else {
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self.dcdc_ena[which as usize] = false;
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i2c.i2c_write(AXP2101_DEV, REG_DCDC_ENA as u8, &[self.encode_dcdc_ena()]).map(|_| ())
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}
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}
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pub fn set_ldo(
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&mut self,
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i2c: &mut dyn i2c::I2cApi,
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setting: Option<f32>,
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which: WhichLdo,
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) -> Result<(), xous::Error> {
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if let Some(voltage) = setting {
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match encode_ldo(voltage, which) {
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Some(code) => {
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self.ldo_v[which as usize] = voltage;
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self.ldo_ena[which as usize] = true;
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let ctl = self.encode_ldo_ena();
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i2c.i2c_write(AXP2101_DEV, (REG_ALDO1_V + which as usize) as u8, &[code]).map(|_| ())?;
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i2c.i2c_write(AXP2101_DEV, REG_LDO1_ENA as u8, &ctl).map(|_| ())
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}
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None => Err(xous::Error::InvalidLimit),
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}
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} else {
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self.ldo_ena[which as usize] = false;
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let ctl = self.encode_ldo_ena();
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i2c.i2c_write(AXP2101_DEV, REG_LDO1_ENA as u8, &ctl).map(|_| ())
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}
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}
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fn encode_dcdc_ena(&self) -> u8 {
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let mut code = 0;
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for (i, &ena) in self.dcdc_ena.iter().enumerate() {
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if ena {
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code |= 1 << i;
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}
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}
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if self.fast_ramp {
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code |= 1 << 5;
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}
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if self.force_ccm {
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code |= 1 << 6;
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}
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code
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}
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fn encode_ldo_ena(&self) -> [u8; 2] {
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let mut ctl = [0u8; 2];
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for (i, &ena) in self.ldo_ena.iter().enumerate() {
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if i < 8 {
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if ena {
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ctl[0] |= 1 << i;
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}
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} else {
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if ena {
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ctl[1] = 1;
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}
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}
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}
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ctl
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}
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}
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pub fn parse_dcdc_ena(d: u8) -> ([bool; 4], bool, bool) {
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let mut enable = [false; 4];
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let mut fast_ramp = false;
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let mut force_ccm = false;
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for (i, ena) in enable.iter_mut().enumerate() {
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if ((d >> i) & 1) == 1 {
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*ena = true;
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}
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}
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if ((d >> 5) & 1) == 1 {
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fast_ramp = true;
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}
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if ((d >> 6) & 1) == 1 {
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force_ccm = true;
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}
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(enable, fast_ramp, force_ccm)
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}
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pub fn encode_dcdc(v: f32, dvm: bool, which: WhichDcDc) -> Option<u8> {
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match which {
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WhichDcDc::Dcdc1 => {
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if v < 1.5 || v > 3.4 {
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None
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} else {
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let code = (v - 1.5) / 0.100;
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return Some(code as u8 | if dvm { 0x80 } else { 0x0 });
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}
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}
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_ => {
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if which == WhichDcDc::Dcdc2 || which == WhichDcDc::Dcdc3 {
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if v < 0.5 || v > 1.54 {
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return None;
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}
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} else if which == WhichDcDc::Dcdc4 {
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if v < 0.5 || v > 1.84 {
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return None;
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}
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} else {
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// we haven't coded the DCDC5 path yet
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return None;
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}
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if v < 1.22 {
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let code = (v - 0.5) / 0.010;
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Some(code as u8)
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} else {
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// high side already bounds checked above
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let code = (v - 1.22) / 0.020;
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Some(code as u8 + 70)
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}
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}
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}
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}
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pub fn parse_dcdc(d: u8, which: WhichDcDc) -> (f32, bool) {
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match which {
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WhichDcDc::Dcdc1 => {
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let step = 0.10f32;
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let dvm = (d & 0x80) != 0;
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let voltage = ((d & 0x3F) as f32) * step + 1.5;
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(voltage, dvm)
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}
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_ => {
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let step = if (d & 0x7F) <= 71 { 0.010f32 } else { 0.020f32 };
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let dvm = (d & 0x80) != 0;
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let voltage = ((d & 0x7F) as f32) * step + 0.5;
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(voltage, dvm)
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}
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}
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}
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pub fn parse_ldo(code: u8, ldo: WhichLdo) -> f32 {
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let step: f32 = ldo.into();
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0.5f32 + (code as f32) * step
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}
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// returns a tuple of (code, register)
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pub fn encode_ldo(v: f32, ldo: WhichLdo) -> Option<u8> {
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let step: f32 = ldo.into();
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if step == 0.10 {
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if v < 0.5 || v > 3.5 {
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return None;
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}
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} else if step == 0.050 {
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if v < 0.5 || v > 1.4 {
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return None;
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}
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}
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Some(((v - 0.5) / step) as u8)
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}
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