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ticktimer: use correct debug port

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Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2020-11-11 16:07:33 +08:00
parent 1a0be47d05
commit b8f69b4a7f
1 changed files with 2 additions and 2 deletions
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4
services/ticktimer-server/src/debug.rs
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@ -48,7 +48,7 @@ impl Uart {
UART resource. Modify in this function as necessary.
*/
let uart = xous::syscall::map_memory(
xous::MemoryAddress::new(utra::server0::HW_SERVER0_BASE),
xous::MemoryAddress::new(utra::server1::HW_SERVER1_BASE),
None,
4096,
xous::MemoryFlags::R | xous::MemoryFlags::W,
@ -59,7 +59,7 @@ impl Uart {
// core::mem::forget(uart);
println!("Allocating IRQ...");
xous::claim_interrupt(utra::server0::SERVER0_IRQ, handle_irq, core::ptr::null_mut::<usize>()).expect("unable to allocate IRQ");
xous::claim_interrupt(utra::server1::SERVER1_IRQ, handle_irq, core::ptr::null_mut::<usize>()).expect("unable to allocate IRQ");
self.enable_rx();
}