mirror of
https://github.com/saymrwulf/xous-core.git
synced 2026-11-15 08:30:02 +00:00
fix reset conditions and straggler debug statements
This commit is contained in:
bunnie
parent
fa3550a30f
commit
b02112b05a
1 changed files with 32 additions and 29 deletions
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@ -36,7 +36,7 @@ const CRG_EVENT_RING_NUM: usize = 1;
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const CRG_ERST_SIZE: usize = 1;
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const CRG_EVENT_RING_SIZE: usize = 128;
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const CRG_EP0_TD_RING_SIZE: usize = 16;
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const CRG_EP_NUM: usize = 4;
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pub const CRG_EP_NUM: usize = 4;
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const CRG_TD_RING_SIZE: usize = 512; // was 1280 in original code. not even sure we need ... 64?
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const CRG_UDC_MAX_BURST: u32 = 15;
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const CRG_UDC_ISO_INTERVAL: u8 = 3;
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@ -1243,10 +1243,6 @@ impl CorigineUsb {
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compiler_fence(Ordering::SeqCst);
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// Set up storage for Endpoint contexts
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#[cfg(feature = "std")]
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log::trace!("Begin init_device_context");
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#[cfg(not(feature = "std"))]
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println!("Begin init_device_context");
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// init device context and ep context, refer to 7.6.2
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self.p_epcx = AtomicPtr::new((self.ifram_base_ptr + CRG_UDC_EPCX_OFFSET) as *mut EpCxS);
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self.p_epcx_len = CRG_EP_NUM * 2 * size_of::<EpCxS>();
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@ -1265,13 +1261,12 @@ impl CorigineUsb {
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// disable 2.0 LPM
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self.csr.wo(U2PORTPMSC, 0);
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#[cfg(feature = "std")]
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log::trace!("USB init done");
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crate::println!("USB hw init done");
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}
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pub fn init_ep0(&mut self) {
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#[cfg(feature = "std")]
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log::trace!("Begin init_ep0");
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#[cfg(feature = "verbose-debug")]
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crate::println!("Begin init_ep0");
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let udc_ep = &mut self.udc_ep[0];
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udc_ep.ep_num = 0;
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@ -1311,15 +1306,7 @@ impl CorigineUsb {
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let cmd_param0: u32 = (udc_ep.tran_ring_info.vaddr.load(Ordering::SeqCst) as u32) & 0xFFFF_FFF0
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| self.csr.ms(CMDPARA0_CMD0_INIT_EP0_DCS, udc_ep.pcs as u32);
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let cmd_param1: u32 = 0;
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#[cfg(feature = "std")]
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{
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log::debug!(
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"ep0 ring dma addr = {:x}",
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udc_ep.tran_ring_info.vaddr.load(Ordering::SeqCst) as usize
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);
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log::debug!("INIT EP0 CMD par0 = {:x} par1 = {:x}", cmd_param0, cmd_param1);
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}
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#[cfg(not(feature = "std"))]
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#[cfg(feature = "verbose-debug")]
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{
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println!("ep0 ring dma addr = {:x}", udc_ep.tran_ring_info.vaddr.load(Ordering::SeqCst) as usize);
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println!("INIT EP0 CMD par0 = {:x} par1 = {:x}", cmd_param0, cmd_param1);
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@ -1329,8 +1316,6 @@ impl CorigineUsb {
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.expect("couldn't issue ep0 init command");
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self.ep0_buf = AtomicPtr::new((self.ifram_base_ptr + CRG_UDC_EP0_BUF_OFFSET) as *mut u8);
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#[cfg(feature = "std")]
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log::trace!("End init_ep0");
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}
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#[cfg(feature = "std")]
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@ -2168,7 +2153,7 @@ pub struct CorigineWrapper {
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/// Tuple is (type of endpoint, max packet size)
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pub ep_meta: [Option<(EpType, usize)>; CRG_EP_NUM],
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pub ep_out_ready: Box<[AtomicBool]>,
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pub address_is_set: AtomicBool,
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pub address_is_set: Arc<AtomicBool>,
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pub event: Option<CrgEvent>,
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}
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#[cfg(feature = "std")]
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@ -2183,7 +2168,7 @@ impl CorigineWrapper {
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.collect::<Vec<_>>()
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.into_boxed_slice(),
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event: None,
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address_is_set: AtomicBool::new(false),
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address_is_set: Arc::new(AtomicBool::new(false)),
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};
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c
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}
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@ -2198,7 +2183,7 @@ impl CorigineWrapper {
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.collect::<Vec<_>>()
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.into_boxed_slice(),
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event: None,
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address_is_set: AtomicBool::new(self.address_is_set.load(Ordering::SeqCst)),
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address_is_set: self.address_is_set.clone(),
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};
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c.ep_meta.copy_from_slice(&self.ep_meta);
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for (dst, src) in c.ep_out_ready.iter().zip(self.ep_out_ready.iter()) {
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@ -2327,7 +2312,7 @@ impl UsbBus for CorigineWrapper {
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let irq_csr = {
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let mut hw = self.core();
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// disable IRQs
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hw.irq_csr.wfo(utralib::utra::irqarray1::EV_ENABLE_USBC_DUPE, 0);
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hw.irq_csr.wo(utralib::utra::irqarray1::EV_ENABLE, 0);
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hw.reset();
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hw.init();
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hw.start();
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@ -2337,7 +2322,7 @@ impl UsbBus for CorigineWrapper {
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};
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// the lock is released, now we can enable irqs
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irq_csr.wo(utralib::utra::irqarray1::EV_PENDING, 0xffff_ffff); // blanket clear
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irq_csr.wfo(utralib::utra::irqarray1::EV_ENABLE_USBC_DUPE, 1);
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irq_csr.wo(utralib::utra::irqarray1::EV_ENABLE, 3); // FIXME: hard coded value that enables CORIGINE_IRQ_MASK | SW_IRQ_MASK
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// TODO -- figure out what this means
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// self.force_reset().ok();
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@ -2530,9 +2515,11 @@ impl UsbBus for CorigineWrapper {
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let ret = if let Some((ptr, len)) = self.core().app_ptr.take() {
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self.ep_out_ready[ep_addr.index()].store(false, Ordering::SeqCst);
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let app_buf = unsafe { core::slice::from_raw_parts(ptr as *const u8, len) };
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if buf.len() > app_buf.len() {
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if buf.len() < app_buf.len() {
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Err(UsbError::BufferOverflow)
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} else {
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#[cfg(feature = "verbose-debug")]
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crate::println!("copy into len {} from len {}", buf.len(), app_buf.len());
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buf[..app_buf.len()].copy_from_slice(app_buf);
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crate::println!(" {:x?}", &buf[..app_buf.len().min(8)]);
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Ok(app_buf.len())
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@ -2681,9 +2668,25 @@ impl UsbBus for CorigineWrapper {
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fn force_reset(&self) -> Result<()> {
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crate::println!(" ******* force_reset");
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// This is the minimum we need to do to restart EP0, but, I think we also need to reset
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// TRB pointers etc. See page 67 of the manual.
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self.core().update_current_speed();
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self.address_is_set.store(false, Ordering::SeqCst);
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for eor in self.ep_out_ready.iter() {
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eor.store(false, Ordering::SeqCst);
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}
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crate::println!(" ******** reset");
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let irq_csr = {
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let mut hw = self.core();
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// disable IRQs
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hw.irq_csr.wo(utralib::utra::irqarray1::EV_ENABLE, 0);
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hw.reset();
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hw.init();
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hw.start();
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hw.update_current_speed();
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// IRQ enable must happen without dependency on the hardware lock
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hw.irq_csr.clone()
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};
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// the lock is released, now we can enable irqs
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irq_csr.wo(utralib::utra::irqarray1::EV_PENDING, 0xffff_ffff); // blanket clear
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irq_csr.wo(utralib::utra::irqarray1::EV_ENABLE, 3); // FIXME: hard coded value that enables CORIGINE_IRQ_MASK | SW_IRQ_MASK
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Ok(())
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}
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