saymrwulf/xous-core
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remove debug.rs from COM

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This commit is contained in:
bunnie 2020-11-27 16:48:57 +08:00
parent f04484abd9
commit a129b48858
2 changed files with 0 additions and 119 deletions
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113
services/com/src/debug.rs
View file

@ -1,113 +0,0 @@
use core::fmt::{Error, Write};
use utralib::generated::*;
#[macro_export]
macro_rules! print
{
($($args:tt)+) => ({
use core::fmt::Write;
let _ = write!(crate::debug::DEFAULT, $($args)+);
});
}
#[macro_export]
macro_rules! println
{
() => ({
print!("\r\n")
});
($fmt:expr) => ({
print!(concat!($fmt, "\r\n"))
});
($fmt:expr, $($args:tt)+) => ({
print!(concat!($fmt, "\r\n"), $($args)+)
});
}
fn handle_irq(irq_no: usize, arg: *mut usize) {
print!("Handling IRQ {} (arg: {:08x}): ", irq_no, arg as usize);
while let Some(c) = crate::debug::DEFAULT.getc() {
print!("{}", c as char);
}
println!();
}
pub struct Uart {}
// this is a hack to bypass an explicit initialization/allocation step for the debug structure
pub static mut DEFAULT_UART_ADDR: *mut usize = 0x0000_0000 as *mut usize;
pub const DEFAULT: Uart = Uart {};
impl Uart {
fn map_uart(&self) {
/*
Note: the memory address and interrupt specified here needs to map to a unique hardware
UART resource. Modify in this function as necessary.
*/
let uart = xous::syscall::map_memory(
xous::MemoryAddress::new(utra::server0::HW_SERVER0_BASE),
None,
4096,
xous::MemoryFlags::R | xous::MemoryFlags::W,
)
.expect("couldn't map debug uart");
unsafe{ DEFAULT_UART_ADDR = uart.as_mut_ptr() as _; }
println!("Mapped UART @ {:08x}", uart.addr.get());
// core::mem::forget(uart);
println!("Allocating IRQ...");
xous::claim_interrupt(utra::server0::SERVER0_IRQ, handle_irq, core::ptr::null_mut::<usize>()).expect("unable to allocate IRQ");
self.enable_rx();
}
pub fn putc(&self, c: u8) {
if cfg!(feature = "debugprint") {
if unsafe{DEFAULT_UART_ADDR} as usize == 0 {
self.map_uart();
}
let mut uart_csr = CSR::new(unsafe{ DEFAULT_UART_ADDR as *mut u32});
// Wait until TXFULL is `0`
while uart_csr.r(utra::uart::TXFULL) != 0 {}
uart_csr.wo(utra::uart::RXTX, c as u32);
}
}
pub fn enable_rx(&self) {
if cfg!(feature = "debugprint") {
let mut uart_csr = CSR::new(unsafe{DEFAULT_UART_ADDR as *mut u32});
uart_csr.rmwf(utra::uart::EV_ENABLE_RX, 1);
}
}
pub fn getc(&self) -> Option<u8> {
if cfg!(feature = "debugprint") {
if unsafe{DEFAULT_UART_ADDR} as usize == 0 {
self.map_uart();
}
let mut uart_csr = CSR::new(unsafe{DEFAULT_UART_ADDR as *mut u32});
match uart_csr.rf(utra::uart::EV_PENDING_RX) {
0 => None,
ack => {
let c = Some(uart_csr.rf(utra::uart::RXTX_RXTX) as u8);
uart_csr.wfo(utra::uart::EV_PENDING_RX, ack);
c
}
}
} else {
None
}
}
}
impl Write for Uart {
fn write_str(&mut self, s: &str) -> Result<(), Error> {
for c in s.bytes() {
self.putc(c);
}
Ok(())
}
}

6
services/com/src/main.rs
View file

@ -1,10 +1,6 @@
#![cfg_attr(target_os = "none", no_std)]
#![cfg_attr(target_os = "none", no_main)]
#[cfg(target_os = "none")]
#[macro_use]
mod debug;
mod api;
use api::Opcode;
@ -56,7 +52,6 @@ mod implementation {
fn handle_irq(_irq_no: usize, arg: *mut usize) {
let xc = unsafe { &mut *(arg as *mut XousCom) };
println!("COM IRQ");
// just clear the pending request, as this is used as a "wait" until request function
xc.csr.wo(utra::com::EV_PENDING, xc.csr.r(utra::com::EV_PENDING));
}
@ -219,7 +214,6 @@ mod implementation {
fn xmain() -> ! {
use crate::implementation::XousCom;
println!("COM Init");
log_server::init_wait().unwrap();
let com_server =