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cleanup some svd name refs to be clearer

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bunnie 2025-09-20 00:42:33 +08:00
parent 93c7329746
commit 8ff7718309
3 changed files with 1 additions and 144 deletions
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0
utralib/bao1x/daric.svd → utralib/bao1x/bao1x_peri.svd
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143
utralib/bao1x/soc.svd
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@ -1,143 +0,0 @@
<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>litex</vendor>
<name>SOC</name>
<description><![CDATA[Litex SoC 2025-07-23 01:19:07]]></description>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>IDENTIFIER_MEM</name>
<baseAddress>0x40080000</baseAddress>
<groupName>IDENTIFIER_MEM</groupName>
<registers>
<register>
<name>IDENTIFIER_MEM</name>
<description><![CDATA[8 x 24-bit memory]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>identifier_mem</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>MAIN</name>
<baseAddress>0x40081000</baseAddress>
<groupName>MAIN</groupName>
<registers>
<register>
<name>DONE</name>
<description><![CDATA[Set to `1` if the simulation should auto-terminate]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>done</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>IRQTEST0</name>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>trigger</name>
<msb>15</msb>
<bitRange>[15:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Triggers for interrupt testing bank 0]]></description>
</field>
</fields>
</register>
<register>
<name>REPORT</name>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>report</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Fast feedback for simulations]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0xc</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
</peripherals>
<vendorExtensions>
<memoryRegions>
<memoryRegion>
<name>RERAM</name>
<baseAddress>0x60000000</baseAddress>
<size>0x00400000</size>
</memoryRegion>
<memoryRegion>
<name>SRAM</name>
<baseAddress>0x61000000</baseAddress>
<size>0x00200000</size>
</memoryRegion>
<memoryRegion>
<name>XIP</name>
<baseAddress>0x70000000</baseAddress>
<size>0x08000000</size>
</memoryRegion>
<memoryRegion>
<name>VEXRISCV_DEBUG</name>
<baseAddress>0xEFFF0000</baseAddress>
<size>0x00001000</size>
</memoryRegion>
<memoryRegion>
<name>CSR</name>
<baseAddress>0x40080000</baseAddress>
<size>0x00040000</size>
</memoryRegion>
</memoryRegions>
<constants>
<constant name="CONFIG_CLOCK_FREQUENCY" value="800000000" />
<constant name="CONFIG_CPU_TYPE_NONE" value="None" />
<constant name="CONFIG_CPU_VARIANT_STANDARD" value="None" />
<constant name="CONFIG_CPU_HUMAN_NAME" value="Unknown" />
<constant name="CONFIG_BIOS_NO_BUILD_TIME" value="None" />
<constant name="CONFIG_CSR_DATA_WIDTH" value="32" />
<constant name="CONFIG_CSR_ALIGNMENT" value="32" />
<constant name="CONFIG_BUS_STANDARD" value="AXI-LITE" />
<constant name="CONFIG_BUS_DATA_WIDTH" value="32" />
<constant name="CONFIG_BUS_ADDRESS_WIDTH" value="32" />
<constant name="CONFIG_BUS_BURSTING" value="0" />
</constants>
</vendorExtensions>
</device>

2
utralib/build.rs
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@ -123,7 +123,7 @@ fn main() {
let generated_filename = "src/generated/atsama5d27.rs";
#[cfg(feature = "bao1x")]
let svd_filenames = vec!["bao1x/core.svd", "bao1x/daric.svd"];
let svd_filenames = vec!["bao1x/core.svd", "bao1x/bao1x_peri.svd"];
#[cfg(feature = "bao1x")]
let generated_filename = "src/generated/bao1x.rs";