mirror of
https://github.com/saymrwulf/xous-core.git
synced 2026-11-15 08:30:02 +00:00
update artifacts with latest generated output
This commit is contained in:
bunnie
parent
28142e2b24
commit
83f5205a2d
4 changed files with 2845 additions and 1698 deletions
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@ -3,7 +3,7 @@
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<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
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<vendor>litex</vendor>
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<name>SOC</name>
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<description><![CDATA[Litex SoC 2024-03-03 02:37:32]]></description>
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<description><![CDATA[Litex SoC 2024-06-25 18:47:30]]></description>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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@ -10312,6 +10312,152 @@ register to disable individual events.]]></description>
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<value>20</value>
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</interrupt>
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</peripheral>
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<peripheral>
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<name>TIMER0</name>
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<baseAddress>0xE001C000</baseAddress>
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<groupName>TIMER0</groupName>
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<registers>
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<register>
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<name>LOAD</name>
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<description><![CDATA[Load value when Timer is (re-)enabled. In One-Shot mode, the value written to
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this register specifies the Timer's duration in clock cycles.]]></description>
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<addressOffset>0x0000</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>load</name>
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<msb>31</msb>
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<bitRange>[31:0]</bitRange>
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<lsb>0</lsb>
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</field>
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</fields>
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</register>
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<register>
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<name>RELOAD</name>
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<description><![CDATA[Reload value when Timer reaches ``0``. In Periodic mode, the value written to
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this register specify the Timer's period in clock cycles.]]></description>
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<addressOffset>0x0004</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>reload</name>
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<msb>31</msb>
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<bitRange>[31:0]</bitRange>
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<lsb>0</lsb>
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</field>
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</fields>
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</register>
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<register>
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<name>EN</name>
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<description><![CDATA[Enable flag of the Timer. Set this flag to ``1`` to enable/start the Timer. Set
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to ``0`` to disable the Timer.]]></description>
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<addressOffset>0x0008</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>en</name>
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<msb>0</msb>
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<bitRange>[0:0]</bitRange>
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<lsb>0</lsb>
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</field>
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</fields>
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</register>
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<register>
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<name>UPDATE_VALUE</name>
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<description><![CDATA[Update trigger for the current countdown value. A write to this register latches
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the current countdown value to ``value`` register.]]></description>
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<addressOffset>0x000c</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>update_value</name>
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<msb>0</msb>
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<bitRange>[0:0]</bitRange>
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<lsb>0</lsb>
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</field>
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</fields>
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</register>
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<register>
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<name>VALUE</name>
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<description><![CDATA[Latched countdown value. This value is updated by writing to ``update_value``.]]></description>
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<addressOffset>0x0010</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>value</name>
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<msb>31</msb>
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<bitRange>[31:0]</bitRange>
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<lsb>0</lsb>
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</field>
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</fields>
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</register>
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<register>
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<name>EV_STATUS</name>
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<description><![CDATA[This register contains the current raw level of the zero event trigger. Writes
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to this register have no effect.]]></description>
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<addressOffset>0x0014</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>zero</name>
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<msb>0</msb>
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<bitRange>[0:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[Level of the ``zero`` event]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>EV_PENDING</name>
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<description><![CDATA[When a zero event occurs, the corresponding bit will be set in this register.
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To clear the Event, set the corresponding bit in this register.]]></description>
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<addressOffset>0x0018</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>zero</name>
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<msb>0</msb>
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<bitRange>[0:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[`1` if a `zero` event occurred. This Event is triggered on a **falling** edge.]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>EV_ENABLE</name>
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<description><![CDATA[This register enables the corresponding zero events. Write a ``0`` to this
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register to disable individual events.]]></description>
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<addressOffset>0x001c</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>zero</name>
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<msb>0</msb>
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<bitRange>[0:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[Write a ``1`` to enable the ``zero`` Event]]></description>
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</field>
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</fields>
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</register>
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</registers>
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<addressBlock>
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<offset>0</offset>
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<size>0x20</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>timer0</name>
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<value>30</value>
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</interrupt>
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</peripheral>
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</peripherals>
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<vendorExtensions>
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<memoryRegions>
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@ -10467,6 +10613,7 @@ register to disable individual events.]]></description>
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<constant name="MB_CLIENT_INTERRUPT" value="23" />
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<constant name="SUSRES_INTERRUPT" value="21" />
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<constant name="TICKTIMER_INTERRUPT" value="20" />
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<constant name="TIMER0_INTERRUPT" value="30" />
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</constants>
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</vendorExtensions>
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</device>
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File diff suppressed because it is too large
Load diff
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@ -3,7 +3,7 @@
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<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
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<vendor>litex</vendor>
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<name>SOC</name>
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<description><![CDATA[Litex SoC 2024-03-03 02:37:34]]></description>
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<description><![CDATA[Litex SoC 2024-06-25 18:47:38]]></description>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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@ -13,523 +13,9 @@
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<resetMask>0xFFFFFFFF</resetMask>
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<peripherals>
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<peripheral>
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<name>GPIO</name>
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<baseAddress>0x40080000</baseAddress>
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<groupName>GPIO</groupName>
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<registers>
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<register>
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<name>UARTSEL</name>
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<description><![CDATA[Used to select which UART is routed to physical pins, 00 = kernel debug, 01 =
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console, others reserved based on build]]></description>
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<addressOffset>0x0000</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>uartsel</name>
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<msb>1</msb>
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<bitRange>[1:0]</bitRange>
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<lsb>0</lsb>
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</field>
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</fields>
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</register>
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</registers>
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<addressBlock>
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<offset>0</offset>
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<size>0x4</size>
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<usage>registers</usage>
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</addressBlock>
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</peripheral>
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<peripheral>
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<name>UART</name>
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<baseAddress>0x40082000</baseAddress>
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<groupName>UART</groupName>
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<registers>
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<register>
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<name>RXTX</name>
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<addressOffset>0x0000</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>rxtx</name>
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<msb>7</msb>
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<bitRange>[7:0]</bitRange>
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<lsb>0</lsb>
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</field>
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</fields>
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</register>
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<register>
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<name>TXFULL</name>
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<description><![CDATA[TX FIFO Full.]]></description>
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<addressOffset>0x0004</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>txfull</name>
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<msb>0</msb>
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<bitRange>[0:0]</bitRange>
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<lsb>0</lsb>
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</field>
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</fields>
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</register>
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<register>
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<name>RXEMPTY</name>
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<description><![CDATA[RX FIFO Empty.]]></description>
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<addressOffset>0x0008</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>rxempty</name>
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<msb>0</msb>
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<bitRange>[0:0]</bitRange>
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<lsb>0</lsb>
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</field>
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</fields>
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</register>
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<register>
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<name>EV_STATUS</name>
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<description><![CDATA[This register contains the current raw level of the rx event trigger. Writes to
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this register have no effect.]]></description>
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<addressOffset>0x000c</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>tx</name>
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<msb>0</msb>
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<bitRange>[0:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[Level of the ``tx`` event]]></description>
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</field>
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<field>
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<name>rx</name>
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<msb>1</msb>
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<bitRange>[1:1]</bitRange>
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<lsb>1</lsb>
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<description><![CDATA[Level of the ``rx`` event]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>EV_PENDING</name>
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<description><![CDATA[When a rx event occurs, the corresponding bit will be set in this register. To
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clear the Event, set the corresponding bit in this register.]]></description>
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<addressOffset>0x0010</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>tx</name>
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<msb>0</msb>
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<bitRange>[0:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[`1` if a `tx` event occurred. This Event is triggered on a **falling** edge.]]></description>
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</field>
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<field>
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<name>rx</name>
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<msb>1</msb>
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<bitRange>[1:1]</bitRange>
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<lsb>1</lsb>
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<description><![CDATA[`1` if a `rx` event occurred. This Event is triggered on a **falling** edge.]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>EV_ENABLE</name>
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<description><![CDATA[This register enables the corresponding rx events. Write a ``0`` to this
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register to disable individual events.]]></description>
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<addressOffset>0x0014</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>tx</name>
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<msb>0</msb>
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<bitRange>[0:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[Write a ``1`` to enable the ``tx`` Event]]></description>
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</field>
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<field>
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<name>rx</name>
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<msb>1</msb>
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<bitRange>[1:1]</bitRange>
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<lsb>1</lsb>
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<description><![CDATA[Write a ``1`` to enable the ``rx`` Event]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>TXEMPTY</name>
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<description><![CDATA[TX FIFO Empty.]]></description>
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<addressOffset>0x0018</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>txempty</name>
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<msb>0</msb>
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<bitRange>[0:0]</bitRange>
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<lsb>0</lsb>
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</field>
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</fields>
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</register>
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<register>
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<name>RXFULL</name>
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<description><![CDATA[RX FIFO Full.]]></description>
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<addressOffset>0x001c</addressOffset>
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<resetValue>0x00</resetValue>
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<size>32</size>
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<fields>
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<field>
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<name>rxfull</name>
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<msb>0</msb>
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<bitRange>[0:0]</bitRange>
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<lsb>0</lsb>
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</field>
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</fields>
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</register>
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</registers>
|
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<addressBlock>
|
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<offset>0</offset>
|
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<size>0x20</size>
|
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<usage>registers</usage>
|
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</addressBlock>
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<interrupt>
|
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<name>uart</name>
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<value>0</value>
|
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</interrupt>
|
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</peripheral>
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<peripheral>
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<name>CONSOLE</name>
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<baseAddress>0x40084000</baseAddress>
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<groupName>CONSOLE</groupName>
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<registers>
|
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<register>
|
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<name>RXTX</name>
|
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<addressOffset>0x0000</addressOffset>
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<resetValue>0x00</resetValue>
|
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<size>32</size>
|
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<fields>
|
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<field>
|
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<name>rxtx</name>
|
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<msb>7</msb>
|
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<bitRange>[7:0]</bitRange>
|
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<lsb>0</lsb>
|
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</field>
|
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</fields>
|
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</register>
|
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<register>
|
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<name>TXFULL</name>
|
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<description><![CDATA[TX FIFO Full.]]></description>
|
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<addressOffset>0x0004</addressOffset>
|
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<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
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<field>
|
||||
<name>txfull</name>
|
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<msb>0</msb>
|
||||
<bitRange>[0:0]</bitRange>
|
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<lsb>0</lsb>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>RXEMPTY</name>
|
||||
<description><![CDATA[RX FIFO Empty.]]></description>
|
||||
<addressOffset>0x0008</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>rxempty</name>
|
||||
<msb>0</msb>
|
||||
<bitRange>[0:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>EV_STATUS</name>
|
||||
<description><![CDATA[This register contains the current raw level of the rx event trigger. Writes to
|
||||
this register have no effect.]]></description>
|
||||
<addressOffset>0x000c</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>tx</name>
|
||||
<msb>0</msb>
|
||||
<bitRange>[0:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[Level of the ``tx`` event]]></description>
|
||||
</field>
|
||||
<field>
|
||||
<name>rx</name>
|
||||
<msb>1</msb>
|
||||
<bitRange>[1:1]</bitRange>
|
||||
<lsb>1</lsb>
|
||||
<description><![CDATA[Level of the ``rx`` event]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>EV_PENDING</name>
|
||||
<description><![CDATA[When a rx event occurs, the corresponding bit will be set in this register. To
|
||||
clear the Event, set the corresponding bit in this register.]]></description>
|
||||
<addressOffset>0x0010</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>tx</name>
|
||||
<msb>0</msb>
|
||||
<bitRange>[0:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[`1` if a `tx` event occurred. This Event is triggered on a **falling** edge.]]></description>
|
||||
</field>
|
||||
<field>
|
||||
<name>rx</name>
|
||||
<msb>1</msb>
|
||||
<bitRange>[1:1]</bitRange>
|
||||
<lsb>1</lsb>
|
||||
<description><![CDATA[`1` if a `rx` event occurred. This Event is triggered on a **falling** edge.]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>EV_ENABLE</name>
|
||||
<description><![CDATA[This register enables the corresponding rx events. Write a ``0`` to this
|
||||
register to disable individual events.]]></description>
|
||||
<addressOffset>0x0014</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>tx</name>
|
||||
<msb>0</msb>
|
||||
<bitRange>[0:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[Write a ``1`` to enable the ``tx`` Event]]></description>
|
||||
</field>
|
||||
<field>
|
||||
<name>rx</name>
|
||||
<msb>1</msb>
|
||||
<bitRange>[1:1]</bitRange>
|
||||
<lsb>1</lsb>
|
||||
<description><![CDATA[Write a ``1`` to enable the ``rx`` Event]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>TXEMPTY</name>
|
||||
<description><![CDATA[TX FIFO Empty.]]></description>
|
||||
<addressOffset>0x0018</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>txempty</name>
|
||||
<msb>0</msb>
|
||||
<bitRange>[0:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>RXFULL</name>
|
||||
<description><![CDATA[RX FIFO Full.]]></description>
|
||||
<addressOffset>0x001c</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>rxfull</name>
|
||||
<msb>0</msb>
|
||||
<bitRange>[0:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x20</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<interrupt>
|
||||
<name>console</name>
|
||||
<value>1</value>
|
||||
</interrupt>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>APP_UART</name>
|
||||
<baseAddress>0x40086000</baseAddress>
|
||||
<groupName>APP_UART</groupName>
|
||||
<registers>
|
||||
<register>
|
||||
<name>RXTX</name>
|
||||
<addressOffset>0x0000</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>rxtx</name>
|
||||
<msb>7</msb>
|
||||
<bitRange>[7:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>TXFULL</name>
|
||||
<description><![CDATA[TX FIFO Full.]]></description>
|
||||
<addressOffset>0x0004</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>txfull</name>
|
||||
<msb>0</msb>
|
||||
<bitRange>[0:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>RXEMPTY</name>
|
||||
<description><![CDATA[RX FIFO Empty.]]></description>
|
||||
<addressOffset>0x0008</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>rxempty</name>
|
||||
<msb>0</msb>
|
||||
<bitRange>[0:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>EV_STATUS</name>
|
||||
<description><![CDATA[This register contains the current raw level of the rx event trigger. Writes to
|
||||
this register have no effect.]]></description>
|
||||
<addressOffset>0x000c</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>tx</name>
|
||||
<msb>0</msb>
|
||||
<bitRange>[0:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[Level of the ``tx`` event]]></description>
|
||||
</field>
|
||||
<field>
|
||||
<name>rx</name>
|
||||
<msb>1</msb>
|
||||
<bitRange>[1:1]</bitRange>
|
||||
<lsb>1</lsb>
|
||||
<description><![CDATA[Level of the ``rx`` event]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>EV_PENDING</name>
|
||||
<description><![CDATA[When a rx event occurs, the corresponding bit will be set in this register. To
|
||||
clear the Event, set the corresponding bit in this register.]]></description>
|
||||
<addressOffset>0x0010</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>tx</name>
|
||||
<msb>0</msb>
|
||||
<bitRange>[0:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[`1` if a `tx` event occurred. This Event is triggered on a **falling** edge.]]></description>
|
||||
</field>
|
||||
<field>
|
||||
<name>rx</name>
|
||||
<msb>1</msb>
|
||||
<bitRange>[1:1]</bitRange>
|
||||
<lsb>1</lsb>
|
||||
<description><![CDATA[`1` if a `rx` event occurred. This Event is triggered on a **falling** edge.]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>EV_ENABLE</name>
|
||||
<description><![CDATA[This register enables the corresponding rx events. Write a ``0`` to this
|
||||
register to disable individual events.]]></description>
|
||||
<addressOffset>0x0014</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>tx</name>
|
||||
<msb>0</msb>
|
||||
<bitRange>[0:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
<description><![CDATA[Write a ``1`` to enable the ``tx`` Event]]></description>
|
||||
</field>
|
||||
<field>
|
||||
<name>rx</name>
|
||||
<msb>1</msb>
|
||||
<bitRange>[1:1]</bitRange>
|
||||
<lsb>1</lsb>
|
||||
<description><![CDATA[Write a ``1`` to enable the ``rx`` Event]]></description>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>TXEMPTY</name>
|
||||
<description><![CDATA[TX FIFO Empty.]]></description>
|
||||
<addressOffset>0x0018</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>txempty</name>
|
||||
<msb>0</msb>
|
||||
<bitRange>[0:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>RXFULL</name>
|
||||
<description><![CDATA[RX FIFO Full.]]></description>
|
||||
<addressOffset>0x001c</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>rxfull</name>
|
||||
<msb>0</msb>
|
||||
<bitRange>[0:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x20</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<interrupt>
|
||||
<name>app_uart</name>
|
||||
<value>2</value>
|
||||
</interrupt>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>IDENTIFIER_MEM</name>
|
||||
<baseAddress>0x40087000</baseAddress>
|
||||
<baseAddress>0x40080000</baseAddress>
|
||||
<groupName>IDENTIFIER_MEM</groupName>
|
||||
<registers>
|
||||
<register>
|
||||
|
|
@ -556,43 +42,13 @@ register to disable individual events.]]></description>
|
|||
</peripheral>
|
||||
<peripheral>
|
||||
<name>MAIN</name>
|
||||
<baseAddress>0x40088000</baseAddress>
|
||||
<baseAddress>0x40081000</baseAddress>
|
||||
<groupName>MAIN</groupName>
|
||||
<registers>
|
||||
<register>
|
||||
<name>REPORT</name>
|
||||
<description><![CDATA[A 32-bit value to report sim state]]></description>
|
||||
<addressOffset>0x0000</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>report</name>
|
||||
<msb>31</msb>
|
||||
<bitRange>[31:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SUCCESS</name>
|
||||
<description><![CDATA[Determines the result code for the simulation. 0 means fail, 1 means pass]]></description>
|
||||
<addressOffset>0x0004</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>success</name>
|
||||
<msb>0</msb>
|
||||
<bitRange>[0:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>DONE</name>
|
||||
<description><![CDATA[Set to `1` if the simulation should auto-terminate]]></description>
|
||||
<addressOffset>0x0008</addressOffset>
|
||||
<addressOffset>0x0000</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
|
|
@ -604,54 +60,9 @@ register to disable individual events.]]></description>
|
|||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>WDATA</name>
|
||||
<description><![CDATA[Write values here to check cache coherence issues]]></description>
|
||||
<addressOffset>0x000c</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>wdata</name>
|
||||
<msb>31</msb>
|
||||
<bitRange>[31:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>RDATA</name>
|
||||
<description><![CDATA[Data readback derived from coherence_w]]></description>
|
||||
<addressOffset>0x0010</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>rdata</name>
|
||||
<msb>31</msb>
|
||||
<bitRange>[31:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>RINC</name>
|
||||
<description><![CDATA[Every time this is read, the base value is incremented by 3]]></description>
|
||||
<addressOffset>0x0014</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
<field>
|
||||
<name>rinc</name>
|
||||
<msb>31</msb>
|
||||
<bitRange>[31:0]</bitRange>
|
||||
<lsb>0</lsb>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>IRQTEST0</name>
|
||||
<addressOffset>0x0018</addressOffset>
|
||||
<addressOffset>0x0004</addressOffset>
|
||||
<resetValue>0x00</resetValue>
|
||||
<size>32</size>
|
||||
<fields>
|
||||
|
|
@ -667,7 +78,7 @@ register to disable individual events.]]></description>
|
|||
</registers>
|
||||
<addressBlock>
|
||||
<offset>0</offset>
|
||||
<size>0x1c</size>
|
||||
<size>0x8</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
</peripheral>
|
||||
|
|
@ -687,7 +98,7 @@ register to disable individual events.]]></description>
|
|||
<memoryRegion>
|
||||
<name>XIP</name>
|
||||
<baseAddress>0x70000000</baseAddress>
|
||||
<size>0x04000000</size>
|
||||
<size>0x08000000</size>
|
||||
</memoryRegion>
|
||||
<memoryRegion>
|
||||
<name>VEXRISCV_DEBUG</name>
|
||||
|
|
@ -712,9 +123,6 @@ register to disable individual events.]]></description>
|
|||
<constant name="CONFIG_BUS_DATA_WIDTH" value="32" />
|
||||
<constant name="CONFIG_BUS_ADDRESS_WIDTH" value="32" />
|
||||
<constant name="CONFIG_BUS_BURSTING" value="0" />
|
||||
<constant name="APP_UART_INTERRUPT" value="2" />
|
||||
<constant name="CONSOLE_INTERRUPT" value="1" />
|
||||
<constant name="UART_INTERRUPT" value="0" />
|
||||
</constants>
|
||||
</vendorExtensions>
|
||||
</device>
|
||||
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue