mirror of
https://github.com/saymrwulf/xous-core.git
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add unit tests for aliased fifo pages
This commit is contained in:
bunnie
parent
7b2109b1cc
commit
7f35fa8e72
2 changed files with 340 additions and 1 deletions
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@ -760,6 +760,239 @@ pub fn fifo_level_tests() -> usize {
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1
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}
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#[derive(Clone, Copy)]
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struct FifoLevelTestAliasConfig {
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tx_reg: crate::Register,
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rx_reg: crate::Register,
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levels: [crate::Field; 2],
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event_masks: [u32; 2],
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event_reg: crate::Register,
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check_level: crate::Field,
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csr: CSR<u32>,
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}
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// Copy of the fifo_level_tests, but using aliased FIFO endpoints for injection and control.
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pub fn fifo_alias_tests() -> usize {
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print!("FIFO level aliases\r");
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// clear prior test config state
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let mut test_cfg = CSR::new(utra::csrtest::HW_CSRTEST_BASE as *mut u32);
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test_cfg.wo(utra::csrtest::WTEST, 0);
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let mut bio_ss = BioSharedState::new();
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// stop all the machines, so that code can be loaded
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bio_ss.bio.wo(utra::bio_bdma::SFR_CTRL, 0x0);
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// let code = fifo_level_tests_code();
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// bio_ss.load_code(code, 0);
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// configure fifo trigger levels
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bio_ss.bio.wfo(utra::bio_bdma::SFR_ELEVEL_FIFO_EVENT_LEVEL0, 0);
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bio_ss.bio.wfo(utra::bio_bdma::SFR_ELEVEL_FIFO_EVENT_LEVEL1, 9);
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bio_ss.bio.wfo(utra::bio_bdma::SFR_ELEVEL_FIFO_EVENT_LEVEL2, 1);
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bio_ss.bio.wfo(utra::bio_bdma::SFR_ELEVEL_FIFO_EVENT_LEVEL3, 8);
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bio_ss.bio.wfo(utra::bio_bdma::SFR_ELEVEL_FIFO_EVENT_LEVEL4, 2);
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bio_ss.bio.wfo(utra::bio_bdma::SFR_ELEVEL_FIFO_EVENT_LEVEL5, 7);
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bio_ss.bio.wfo(utra::bio_bdma::SFR_ELEVEL_FIFO_EVENT_LEVEL6, 4);
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bio_ss.bio.wfo(utra::bio_bdma::SFR_ELEVEL_FIFO_EVENT_LEVEL7, 4);
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// configure the polarities
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bio_ss.bio.wfo(utra::bio_bdma::SFR_ETYPE_FIFO_EVENT_EQ_MASK, 0b11_00_11_11);
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bio_ss.bio.rmwf(utra::bio_bdma::SFR_ETYPE_FIFO_EVENT_LT_MASK, 0b11_01_01_00);
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bio_ss.bio.rmwf(utra::bio_bdma::SFR_ETYPE_FIFO_EVENT_GT_MASK, 0b10_10_10_00);
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/*
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The structure of the FIFO events is that there are two event level configurations
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per FIFO, structured as fifo [N] gets event level [N*2, N*2+1].
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Each event level could trigger on equals, less than, greater than, or any combination
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of the three.
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*/
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let mut fifo_test_configs: [FifoLevelTestAliasConfig; 4] = [
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FifoLevelTestAliasConfig {
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tx_reg: utra::bio_fifo0::SFR_TXF0,
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rx_reg: utra::bio_fifo0::SFR_RXF0,
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levels: [
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utra::bio_bdma::SFR_ELEVEL_FIFO_EVENT_LEVEL0,
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utra::bio_bdma::SFR_ELEVEL_FIFO_EVENT_LEVEL1,
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],
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event_masks: [0x1, 0x2],
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event_reg: utra::bio_fifo0::SFR_EVENT_STATUS,
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check_level: utra::bio_fifo0::SFR_FLEVEL_PCLK_REGFIFO_LEVEL0,
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csr: CSR::new(utra::bio_fifo0::HW_BIO_FIFO0_BASE as *mut u32),
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},
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FifoLevelTestAliasConfig {
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tx_reg: utra::bio_fifo1::SFR_TXF1,
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rx_reg: utra::bio_fifo1::SFR_RXF1,
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levels: [
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utra::bio_bdma::SFR_ELEVEL_FIFO_EVENT_LEVEL2,
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utra::bio_bdma::SFR_ELEVEL_FIFO_EVENT_LEVEL3,
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],
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event_masks: [0x4, 0x8],
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event_reg: utra::bio_fifo1::SFR_EVENT_STATUS,
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check_level: utra::bio_fifo1::SFR_FLEVEL_PCLK_REGFIFO_LEVEL1,
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csr: CSR::new(utra::bio_fifo1::HW_BIO_FIFO1_BASE as *mut u32),
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},
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FifoLevelTestAliasConfig {
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tx_reg: utra::bio_fifo2::SFR_TXF2,
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rx_reg: utra::bio_fifo2::SFR_RXF2,
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levels: [
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utra::bio_bdma::SFR_ELEVEL_FIFO_EVENT_LEVEL4,
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utra::bio_bdma::SFR_ELEVEL_FIFO_EVENT_LEVEL5,
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],
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event_masks: [0x10, 0x20],
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event_reg: utra::bio_fifo2::SFR_EVENT_STATUS,
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check_level: utra::bio_fifo2::SFR_FLEVEL_PCLK_REGFIFO_LEVEL2,
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csr: CSR::new(utra::bio_fifo2::HW_BIO_FIFO2_BASE as *mut u32),
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},
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FifoLevelTestAliasConfig {
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tx_reg: utra::bio_fifo3::SFR_TXF3,
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rx_reg: utra::bio_fifo3::SFR_RXF3,
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levels: [
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utra::bio_bdma::SFR_ELEVEL_FIFO_EVENT_LEVEL6,
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utra::bio_bdma::SFR_ELEVEL_FIFO_EVENT_LEVEL7,
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],
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event_masks: [0x40, 0x80],
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event_reg: utra::bio_fifo3::SFR_EVENT_STATUS,
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check_level: utra::bio_fifo3::SFR_FLEVEL_PCLK_REGFIFO_LEVEL3,
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csr: CSR::new(utra::bio_fifo3::HW_BIO_FIFO3_BASE as *mut u32),
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},
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];
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const FIFO_MAX: u32 = 3; // improve runtime by shortening this test - just want to exercise registers, not all cases
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let mut rx_checks = [0u32; FIFO_MAX as usize];
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let mut tx_state = 0x1;
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let irq_masks: [Register; 4] = [
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utra::bio_bdma::SFR_IRQMASK_0,
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utra::bio_bdma::SFR_IRQMASK_1,
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utra::bio_bdma::SFR_IRQMASK_2,
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utra::bio_bdma::SFR_IRQMASK_3,
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];
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let irqarray18 = CSR::new(utra::irqarray18::HW_IRQARRAY18_BASE as *mut u32);
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for (bank, config) in fifo_test_configs.iter_mut().enumerate() {
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let irq_mask_reg = irq_masks[bank];
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let irq_mask = (1 << bank) as u32;
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print!("irq_mask {:x}\r", irq_mask);
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// we want to check that less than, equals, and greater than triggers work individually
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// then we want to check that lt+eq and gt+eq work together
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// lt+gt trigger doesn't make sense, we just don't check that
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for (&level, &mask) in config.levels.iter().zip(config.event_masks.iter()) {
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bio_ss.bio.wo(irq_mask_reg, mask << 24);
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// reset all the fifos
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bio_ss.bio.wo(utra::bio_bdma::SFR_FIFO_CLR, 0xF);
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for test_level in 0..FIFO_MAX {
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print!("test_level {:x} bank {:x}\r", test_level, bank);
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// test eq at level
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bio_ss.bio.wfo(level, test_level);
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bio_ss.bio.rmwf(SFR_ETYPE_FIFO_EVENT_EQ_MASK, mask);
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bio_ss.bio.rmwf(SFR_ETYPE_FIFO_EVENT_LT_MASK, 0);
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bio_ss.bio.rmwf(SFR_ETYPE_FIFO_EVENT_GT_MASK, 0);
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// fill
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for check_level in 0..FIFO_MAX {
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let ev_check = config.csr.r(config.event_reg) >> 24;
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// report_api(ev_check);
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if check_level == test_level {
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assert!(ev_check & mask == mask);
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// report_api(irqarray18.r(utra::irqarray18::EV_STATUS));
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assert!(irqarray18.r(utra::irqarray18::EV_STATUS) & irq_mask == irq_mask);
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} else {
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assert!(ev_check & mask != mask);
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// report_api(irqarray18.r(utra::irqarray18::EV_STATUS));
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assert!(irqarray18.r(utra::irqarray18::EV_STATUS) & irq_mask != irq_mask);
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}
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assert!(check_level == config.csr.rf(config.check_level));
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config.csr.wo(config.tx_reg, tx_state);
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// report_api(tx_state);
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rx_checks[check_level as usize] = tx_state;
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tx_state = crate::lfsr_next_u32(tx_state);
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}
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// drain
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// report_api(0xdddd_dddd);
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for check_level in 0..FIFO_MAX {
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let rx = config.csr.r(config.rx_reg);
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// report_api(rx);
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assert!(rx == rx_checks[check_level as usize]);
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let ev_check = config.csr.r(config.event_reg) >> 24;
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if FIFO_MAX - check_level - 1 == test_level {
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assert!(ev_check & mask == mask);
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assert!(irqarray18.r(utra::irqarray18::EV_STATUS) & irq_mask == irq_mask);
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} else {
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assert!(ev_check & mask != mask);
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assert!(irqarray18.r(utra::irqarray18::EV_STATUS) & irq_mask != irq_mask);
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}
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}
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// test lt at level
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bio_ss.bio.wfo(level, test_level);
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bio_ss.bio.rmwf(SFR_ETYPE_FIFO_EVENT_EQ_MASK, 0);
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bio_ss.bio.rmwf(SFR_ETYPE_FIFO_EVENT_LT_MASK, mask);
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bio_ss.bio.rmwf(SFR_ETYPE_FIFO_EVENT_GT_MASK, 0);
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// fill
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for check_level in 0..FIFO_MAX {
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let ev_check = config.csr.r(config.event_reg) >> 24;
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if check_level < test_level {
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assert!(ev_check & mask == mask);
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assert!(irqarray18.r(utra::irqarray18::EV_STATUS) & irq_mask == irq_mask);
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} else {
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assert!(ev_check & mask != mask);
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assert!(irqarray18.r(utra::irqarray18::EV_STATUS) & irq_mask != irq_mask);
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}
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config.csr.wo(config.tx_reg, tx_state);
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rx_checks[check_level as usize] = tx_state;
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tx_state = crate::lfsr_next_u32(tx_state);
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}
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// drain
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for check_level in 0..FIFO_MAX {
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let rx = config.csr.r(config.rx_reg);
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assert!(rx == rx_checks[check_level as usize]);
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let ev_check = config.csr.r(config.event_reg) >> 24;
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if FIFO_MAX - check_level - 1 < test_level {
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assert!(ev_check & mask == mask);
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assert!(irqarray18.r(utra::irqarray18::EV_STATUS) & irq_mask == irq_mask);
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} else {
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assert!(ev_check & mask != mask);
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assert!(irqarray18.r(utra::irqarray18::EV_STATUS) & irq_mask != irq_mask);
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}
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}
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// test gt at level ** TEST USING MAIN BANK NOT ALIAS **
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bio_ss.bio.wfo(level, test_level);
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bio_ss.bio.rmwf(SFR_ETYPE_FIFO_EVENT_EQ_MASK, 0);
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bio_ss.bio.rmwf(SFR_ETYPE_FIFO_EVENT_LT_MASK, 0);
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bio_ss.bio.rmwf(SFR_ETYPE_FIFO_EVENT_GT_MASK, mask);
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// fill
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for check_level in 0..FIFO_MAX {
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let ev_check = bio_ss.bio.r(config.event_reg) >> 24;
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if check_level > test_level {
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assert!(ev_check & mask == mask);
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assert!(irqarray18.r(utra::irqarray18::EV_STATUS) & irq_mask == irq_mask);
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} else {
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assert!(ev_check & mask != mask);
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assert!(irqarray18.r(utra::irqarray18::EV_STATUS) & irq_mask != irq_mask);
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}
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bio_ss.bio.wo(config.tx_reg, tx_state);
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rx_checks[check_level as usize] = tx_state;
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tx_state = crate::lfsr_next_u32(tx_state);
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}
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// drain
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for check_level in 0..FIFO_MAX {
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let rx = bio_ss.bio.r(config.rx_reg);
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assert!(rx == rx_checks[check_level as usize]);
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let ev_check = bio_ss.bio.r(config.event_reg) >> 24;
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if FIFO_MAX - check_level - 1 > test_level {
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assert!(ev_check & mask == mask);
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assert!(irqarray18.r(utra::irqarray18::EV_STATUS) & irq_mask == irq_mask);
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} else {
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assert!(ev_check & mask != mask);
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assert!(irqarray18.r(utra::irqarray18::EV_STATUS) & irq_mask != irq_mask);
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}
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}
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}
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bio_ss.bio.wo(irq_mask_reg, 0);
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// other cases not covered, this focuses on aliases, not correctness of all comparison cases
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}
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}
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print!("===FIFO level alias PASS===\r");
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1
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}
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pub fn aclk_tests() -> usize {
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print!("ACLK test\r");
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// clear any prior test config state
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@ -813,3 +1046,109 @@ bio_code!(aclk_code, ACLK_START, ACLK_END,
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"mv x20, x0",
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"mv x17, x31"
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);
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#[derive(Clone, Copy)]
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struct EventAliasConfig {
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event_set: crate::Register,
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event_clr: crate::Register,
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event_status: crate::Register,
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csr: CSR<u32>,
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}
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pub fn event_aliases() -> usize {
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print!("Event aliases test\r");
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let mut event_test_configs: [EventAliasConfig; 4] = [
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EventAliasConfig {
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event_set: utra::bio_fifo0::SFR_EVENT_SET,
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event_clr: utra::bio_fifo0::SFR_EVENT_CLR,
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event_status: utra::bio_fifo0::SFR_EVENT_STATUS,
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csr: CSR::new(utra::bio_fifo0::HW_BIO_FIFO0_BASE as *mut u32),
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},
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EventAliasConfig {
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event_set: utra::bio_fifo1::SFR_EVENT_SET,
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event_clr: utra::bio_fifo1::SFR_EVENT_CLR,
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event_status: utra::bio_fifo1::SFR_EVENT_STATUS,
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csr: CSR::new(utra::bio_fifo1::HW_BIO_FIFO1_BASE as *mut u32),
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},
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EventAliasConfig {
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event_set: utra::bio_fifo2::SFR_EVENT_SET,
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event_clr: utra::bio_fifo2::SFR_EVENT_CLR,
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event_status: utra::bio_fifo2::SFR_EVENT_STATUS,
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csr: CSR::new(utra::bio_fifo2::HW_BIO_FIFO2_BASE as *mut u32),
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},
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EventAliasConfig {
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event_set: utra::bio_fifo3::SFR_EVENT_SET,
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event_clr: utra::bio_fifo3::SFR_EVENT_CLR,
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event_status: utra::bio_fifo3::SFR_EVENT_STATUS,
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csr: CSR::new(utra::bio_fifo3::HW_BIO_FIFO3_BASE as *mut u32),
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},
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];
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// stop machine & load code
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let mut bio_ss = BioSharedState::new();
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bio_ss.bio.wo(utra::bio_bdma::SFR_CTRL, 0x0);
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bio_ss.load_code(event_alias_test_helper(), 0, BioCore::Core0);
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// clear all events
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bio_ss.bio.wfo(utra::bio_bdma::SFR_EVENT_CLR_SFR_EVENT_CLR, 0xFFFF_FF);
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// start core 1
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bio_ss.bio.wo(utra::bio_bdma::SFR_CTRL, 0x111);
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let mut tp = crate::bio_tests::dma::TestPattern::new(Some(0));
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let mut passing = 1;
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for (i, config) in event_test_configs.iter_mut().enumerate() {
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print!(" Checking bank {}...\r", i);
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for _ in 0..3 {
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// clear all events
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bio_ss.bio.wfo(utra::bio_bdma::SFR_EVENT_CLR_SFR_EVENT_CLR, 0xFFFF_FF);
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// get a random state
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let test = tp.next() & 0xFF_FFFF;
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// skip tests where no bits are set in the lower byte, as "something" there is needed to trigger
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// the test
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if test & 0xFF == 0 {
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continue;
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}
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config.csr.wo(config.event_set, test);
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while config.csr.r(config.event_status) & 0xFF != 0 { // check status with the bank register
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// wait for the core to have done its thing
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}
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let result = bio_ss.bio.r(config.event_status); // read result using the base register
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let expected = ((test & 0xFF) << 8) | ((test & 0xFF_FF00) & !((test & 0xFF) << 16));
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if (result & 0xFF_FFFF) != expected {
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print!("got: {:x} expect {:x}\r", result, expected);
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passing = 0;
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}
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// test clearing from host bank
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let next = tp.next() & 0xFFFF00;
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config.csr.wo(config.event_clr, next);
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let result_clr = config.csr.r(config.event_status);
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let expected_clr = result & !next;
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if result_clr != expected_clr {
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print!("clr got: {:x} expect {:x}\r", result_clr, expected_clr);
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passing = 0;
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};
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}
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}
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print!("Event aliases finished\r");
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passing
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}
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#[rustfmt::skip]
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bio_code!(
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event_alias_test_helper,
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EVENT_ALIAS_TEST_HELPER_START,
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EVENT_ALIAS_TEST_HELPER_END,
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"20:",
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"li a0, 0xFF", // event bit 1; a0 is now also event mask
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"mv x27, a0", // set event mask
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"22:",
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"mv t0, x30", // wait for event
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"and t1, t0, a0", // mask event
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"slli t1, t1, 8", // take the event that arrived on [7:0] and set bits in [15:8] based on the event
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"mv x28, t1",
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"and t1, t0, a0", // re-compute the mask because it was overwritten
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"slli t1, t1, 16", // ...and clear bits in [23:16] based on the event
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"mv x29, t1",
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"and t1, t0, a0", // re-compute the mask because it was overwritten
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"mv x29, t1", // clear the incoming event bits that were bits [7:0] to signal that we're done
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"j 22b"
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);
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@ -25,7 +25,7 @@
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//! - x27 -/w mask event sensitivity bits
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//! - x28 -/w `1` will set the corresponding event bit. Only [23:0] are wired up.
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//! - x29 -/w `1` will clear the corresponding event bit Only [23:0] are wired up.
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//! - x30 r/- halt until ((x27 & events) == x27), and return unmasked `events` value
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//! - x30 r/- halt until ((x27 & events) != 0), and return unmasked `events` value
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//!
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//! Core ID & debug:
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//! - x31 r/- [31:30] -> core ID; [29:0] -> cpu clocks since reset
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Reference in a new issue