mirror of
https://github.com/saymrwulf/xous-core.git
synced 2026-11-15 08:30:02 +00:00
endpoint enumeration now working
turns out that you *have* to enable the endpoints after your address has been assigned. You can't do it before. Very subtle one-liner in the docs that I missed until now. :-/
This commit is contained in:
bunnie
parent
f004c45f2a
commit
7b2804eec5
1 changed files with 68 additions and 61 deletions
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@ -17,8 +17,21 @@ use utralib::generated::*;
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#[cfg(not(feature = "std"))]
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use super::compat::AtomicCsr;
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#[cfg(not(feature = "std"))]
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use crate::print;
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use crate::println;
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use crate::usb::utra::*;
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use crate::{print, println};
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// Directional nomenclature.
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//
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// Manual says "outbound" means outbound packets from device going to host. This is an IN packet in USB.
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// "inbound" means inbound packets to device, coming from host. This is the OUT packet in USB.
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pub const USB_SEND: bool = false; // USB IN -> corigine USB_SEND (outbound) -> 0/even on PEI
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pub const USB_RECV: bool = true; // USB OUT -> corigine USB_RECV (inbound) -> 1/odd on PEI
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// these names are picked so that the boolean value maps to the same thing in the reference code
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// this effectively does the "reversal of direction" from USB spec to corigine speak
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pub const CRG_IN: bool = false;
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pub const CRG_OUT: bool = true;
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const CRG_EVENT_RING_NUM: usize = 1;
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const CRG_ERST_SIZE: usize = 1;
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@ -63,9 +76,6 @@ pub const CRG_UDC_TOTAL_MEM_LEN: usize = CRG_UDC_APP_BUFOFFSET + CRG_UDC_APP_BUF
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const MAX_TRB_XFER_LEN: usize = 64 * 1024;
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pub const HOST_SEND: bool = false; // OUT; USB_SEND -> 0/even on PEI
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pub const HOST_RECV: bool = true; // IN; USB_RECV -> 1/odd on PEI
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#[cfg(feature = "std")]
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static INTERRUPT_INIT_DONE: AtomicBool = AtomicBool::new(false);
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@ -579,7 +589,7 @@ pub struct EpCxS {
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impl EpCxS {
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pub fn epcx_setup(&mut self, udc_ep: &UdcEp) {
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// corigine gadget dir should be opposite to host dir
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let ep_type = if udc_ep.direction == HOST_SEND {
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let ep_type = if udc_ep.direction == USB_RECV {
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// transforms the base type into INBOUND
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EpType::try_from(udc_ep.ep_type as u8 + EpType::Invalid2 as u8).unwrap()
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} else {
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@ -705,7 +715,7 @@ impl Default for UdcEp {
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fn default() -> Self {
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Self {
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ep_num: 0,
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direction: HOST_RECV,
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direction: USB_RECV,
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ep_type: EpType::ControlOrInvalid,
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max_packet_size: 0,
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tran_ring_info: BufferInfo::default(),
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@ -1108,7 +1118,7 @@ impl CorigineUsb {
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let udc_ep = &mut self.udc_ep[0];
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udc_ep.ep_num = 0;
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udc_ep.direction = HOST_RECV;
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udc_ep.direction = USB_SEND;
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udc_ep.ep_type = EpType::ControlOrInvalid;
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udc_ep.max_packet_size = 64;
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@ -1477,7 +1487,7 @@ impl CorigineUsb {
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if pei == 0 {
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if comp_code == CompletionCode::Success {
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// ep0_xfer_complete
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if dir == HOST_SEND {
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if dir == USB_SEND {
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ret = CrgEvent::Data(0, 1, 0); // FIXME: this ordering contradicts the `dir` bit, but seems necessary to trigger the next packet send
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} else {
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ret = CrgEvent::Data(1, 0, 0); // FIXME: this ordering contradicts the `dir` bit, but seems necessary to trigger the next packet send
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@ -1490,10 +1500,10 @@ impl CorigineUsb {
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} else if pei >= 2 {
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if comp_code == CompletionCode::Success || comp_code == CompletionCode::ShortPacket {
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#[cfg(feature = "std")]
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log::info!("EP{} xfer event, dir {}", ep_num, if dir { "IN" } else { "OUT" });
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log::info!("EP{} xfer event, dir {}", ep_num, if dir { "OUT" } else { "IN" });
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// xfer_complete
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if dir == HOST_SEND {
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let addr = self.get_app_buf_ptr(ep_num, HOST_SEND);
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if dir == CRG_OUT {
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let addr = self.get_app_buf_ptr(ep_num, dir);
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let hw_buf = unsafe {
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core::slice::from_raw_parts_mut(addr as *mut u8, CRG_UDC_APP_BUF_LEN)
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};
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@ -1590,7 +1600,7 @@ impl CorigineUsb {
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compiler_fence(Ordering::SeqCst);
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self.csr.wfo(DOORBELL_TARGET, 0);
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}
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enq_pt.control_status_trb(pcs, false, false, tag, CRG_INT_TARGET, HOST_RECV);
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enq_pt.control_status_trb(pcs, false, false, tag, CRG_INT_TARGET, USB_RECV);
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let (_enq_pt, _pcs) = self.udc_ep[0].increment_enq_pt();
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self.knock_doorbell(0);
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println!("ep0 sent");
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@ -1657,7 +1667,7 @@ impl CorigineUsb {
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let udc_ep = &mut self.udc_ep[0];
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let enq_pt =
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unsafe { udc_ep.enq_pt.load(Ordering::SeqCst).as_mut().expect("couldn't deref pointer") };
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enq_pt.control_status_trb(udc_ep.pcs, true, false, self.setup_tag, target, HOST_SEND);
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enq_pt.control_status_trb(udc_ep.pcs, true, false, self.setup_tag, target, USB_SEND);
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// TODO: fix raw pointer manips with something more sane?
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let (_enq_pt, _pcs) = udc_ep.increment_enq_pt();
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@ -1766,7 +1776,7 @@ impl CorigineUsb {
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(enq_pt, pcs) = udc_ep.increment_enq_pt();
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}
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enq_pt.control_status_trb(pcs, false, false, tag, intr_target, HOST_RECV);
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enq_pt.control_status_trb(pcs, false, false, tag, intr_target, USB_RECV);
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let (_enq_pt, _pcs) = udc_ep.increment_enq_pt();
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compiler_fence(Ordering::SeqCst);
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@ -1796,7 +1806,7 @@ impl CorigineUsb {
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let udc_ep = &mut self.udc_ep[0];
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let enq_pt =
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unsafe { udc_ep.enq_pt.load(Ordering::SeqCst).as_mut().expect("couldn't deref pointer") };
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enq_pt.control_status_trb(udc_ep.pcs, false, stall, self.setup_tag, intr_target, HOST_RECV);
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enq_pt.control_status_trb(udc_ep.pcs, false, stall, self.setup_tag, intr_target, USB_RECV);
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let (_, _) = udc_ep.increment_enq_pt();
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self.knock_doorbell(0);
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}
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@ -1805,7 +1815,7 @@ impl CorigineUsb {
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let udc_ep = &mut self.udc_ep[0];
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let enq_pt =
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unsafe { udc_ep.enq_pt.load(Ordering::SeqCst).as_mut().expect("couldn't deref pointer") };
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enq_pt.control_status_trb(udc_ep.pcs, false, stall, self.setup_tag, intr_target, HOST_SEND);
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enq_pt.control_status_trb(udc_ep.pcs, false, stall, self.setup_tag, intr_target, USB_SEND);
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let (_, _) = udc_ep.increment_enq_pt();
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self.knock_doorbell(0);
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}
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@ -1940,7 +1950,7 @@ impl CorigineUsb {
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"udc_ep->PEI = {}, xfer ring addr {:x}, dir {}, mps: {}",
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pei,
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vaddr,
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if dir { "IN" } else { "OUT" },
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if dir { "OUT" } else { "IN" },
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max_packet_size,
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);
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assert!(
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@ -1980,7 +1990,7 @@ impl CorigineUsb {
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epcx.epcx_setup(&udc_ep);
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#[cfg(feature = "std")]
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log::info!(
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"dcbap {:x}/{:x}; ecpx * {:x}; epcx: {:x?}",
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"dcbap {:x}/{:x}; ecpx *{:x}; epcx: {:x?}",
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self.csr.r(DCBAPHI),
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self.csr.r(DCBAPLO),
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epcx as *const EpCxS as usize,
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@ -1988,8 +1998,7 @@ impl CorigineUsb {
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);
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self.issue_command(CmdType::ConfigEp, 1 << pei as u32, 0).expect("couldn't issue command");
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self.udc_ep[pei].ep_state = EpState::Running;
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#[cfg(feature = "std")]
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log::info!("config ep and start, PEI = {}", pei);
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#[cfg(feature = "std")]
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log::info!("waiting for EP to go to enabled, baseline: {:x}, epcx: {:x?}", baseline_enable, epcx);
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loop {
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@ -2009,7 +2018,7 @@ impl CorigineUsb {
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pub fn ep_disable(&mut self, ep_num: u8, dir: bool) {
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#[cfg(feature = "std")]
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log::info!("Disable ep {}, dir {}", ep_num, if dir { "IN " } else { "OUT" });
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log::info!("Disable ep {}, dir {}", ep_num, if dir { "OUT" } else { "IN" });
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let pei = 2 * ep_num as usize + if dir { 1 } else { 0 };
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let param0 = 1 << pei as u32;
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if param0 & self.csr.r(EPRUNNING) != 0 {
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@ -2139,7 +2148,7 @@ impl CorigineWrapper {
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txn_offset: Arc::new(Mutex::new([0; CRG_EP_NUM + 1])),
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};
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// ep0 is allocated by default
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c.free_ep[0] = Some((HOST_SEND, 8, EpType::ControlOrInvalid));
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c.free_ep[0] = Some((USB_SEND, 8, EpType::ControlOrInvalid));
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c
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}
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@ -2150,7 +2159,7 @@ impl CorigineWrapper {
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txn_offset: Arc::new(Mutex::new([0; CRG_EP_NUM + 1])),
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};
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// ep0 is allocated by default
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c.free_ep[0] = Some((HOST_SEND, 8, EpType::ControlOrInvalid));
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c.free_ep[0] = Some((USB_SEND, 8, EpType::ControlOrInvalid));
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c
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}
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@ -2195,8 +2204,8 @@ impl UsbBus for CorigineWrapper {
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) -> Result<EndpointAddress> {
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log::info!("alloc_ep {:?} size: {} dir: {:?}", ep_addr, max_packet_size, ep_dir);
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let dir = match ep_dir {
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UsbDirection::Out => HOST_SEND,
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UsbDirection::In => HOST_RECV,
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UsbDirection::Out => CRG_OUT,
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UsbDirection::In => CRG_IN,
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};
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let hw_ep_type = match ep_type {
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EndpointType::Control => EpType::ControlOrInvalid,
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@ -2255,6 +2264,35 @@ impl UsbBus for CorigineWrapper {
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fn set_device_address(&self, addr: u8) {
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log::debug!(" ******** set address");
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self.hw.lock().unwrap().set_addr(addr, CRG_INT_TARGET);
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// this core has a quirk that you can't actually enable the endpoints until *after* the address
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// has been set. :-/
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for (index, &maybe_ep) in self.free_ep.iter().enumerate() {
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if index == 0 {
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continue;
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}
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if let Some((dir, max_packet_size, hw_ep_type)) = maybe_ep {
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self.core().ep_enable(index as u8, dir, max_packet_size, hw_ep_type);
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if dir == CRG_OUT {
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let addr = self.core().get_app_buf_ptr(index as u8, dir);
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// TODO: how do we deal with bulk endpoints??
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self.core().intr_xfer(
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index as u8,
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dir,
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addr,
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CRG_UDC_APP_BUF_LEN,
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CRG_INT_TARGET,
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false,
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false,
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);
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}
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} else {
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self.core().ep_disable(index as u8, true);
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self.core().ep_disable(index as u8, false);
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}
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}
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log::info!("enabled EPs: {:x}", self.core().csr.r(EPENABLE));
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log::info!("running EPs: {:x}", self.core().csr.r(EPRUNNING));
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}
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/// Writes a single packet of data to the specified endpoint and returns number of bytes
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@ -2306,13 +2344,13 @@ impl UsbBus for CorigineWrapper {
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buf.len(),
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&buf[..8.min(buf.len())]
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);
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let addr = self.core().get_app_buf_ptr(ep_addr.index() as u8, HOST_RECV);
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let addr = self.core().get_app_buf_ptr(ep_addr.index() as u8, USB_RECV);
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let hw_buf = unsafe { core::slice::from_raw_parts_mut(addr as *mut u8, CRG_UDC_APP_BUF_LEN) };
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assert!(buf.len() < CRG_UDC_APP_BUF_LEN, "write buffer size exceeded");
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hw_buf[..buf.len()].copy_from_slice(&buf);
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self.core().intr_xfer(
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ep_addr.index() as u8,
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HOST_RECV,
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USB_RECV,
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addr,
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buf.len(),
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CRG_INT_TARGET,
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@ -2438,41 +2476,10 @@ impl UsbBus for CorigineWrapper {
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/// simulating a disconnect or it has not been enabled at creation time.
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fn force_reset(&self) -> Result<()> {
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log::info!(" ******* force_reset");
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/*
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self.core().reset();
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self.core().init();
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self.core().start();
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// This is the minimum we need to do to restart EP0, but, I think we also need to reset
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// TRB pointers etc. See page 67 of the manual.
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self.core().update_current_speed();
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*/
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for (index, &maybe_ep) in self.free_ep.iter().enumerate() {
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log::info!("Resetting EP{}", index);
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if index == 0 {
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// EP0 -> reset & start the machine. Happens before the code below.
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self.core().update_current_speed();
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} else {
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if let Some((dir, max_packet_size, hw_ep_type)) = maybe_ep {
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self.core().ep_enable(index as u8, dir, max_packet_size, hw_ep_type);
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if dir == HOST_SEND {
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let addr = self.core().get_app_buf_ptr(index as u8, dir);
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// TODO: how do we deal with bulk endpoints??
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self.core().intr_xfer(
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index as u8,
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dir,
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addr,
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CRG_UDC_APP_BUF_LEN,
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CRG_INT_TARGET,
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false,
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false,
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);
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}
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} else {
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self.core().ep_disable(index as u8, true);
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self.core().ep_disable(index as u8, false);
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}
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}
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}
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log::info!("enabled EPs: {:x}", self.core().csr.r(EPENABLE));
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log::info!("running EPs: {:x}", self.core().csr.r(EPRUNNING));
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Ok(())
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}
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