diff --git a/emulation/renode.svd b/emulation/renode.svd index 05752ca97..8e593f540 100644 --- a/emulation/renode.svd +++ b/emulation/renode.svd @@ -81,7 +81,7 @@ to the Wishbone/CSR bus are working correctly. The initial reset value of IDENTIFIER_MEM - + 0x0000 0x00 32 @@ -436,8 +436,8 @@ the current countdown value to ``value`` register.]]> output - 5 - [5:0] + 7 + [7:0] 0 @@ -452,8 +452,8 @@ the current countdown value to ``value`` register.]]> input - 5 - [5:0] + 7 + [7:0] 0 @@ -468,8 +468,8 @@ the current countdown value to ``value`` register.]]> drive - 5 - [5:0] + 7 + [7:0] 0 @@ -484,8 +484,8 @@ the current countdown value to ``value`` register.]]> intena - 5 - [5:0] + 7 + [7:0] 0 @@ -501,8 +501,8 @@ interrupts.]]> intpol - 5 - [5:0] + 7 + [7:0] 0 @@ -533,8 +533,8 @@ console, others undefined]]> status - 5 - [5:0] + 7 + [7:0] 0 @@ -548,8 +548,8 @@ console, others undefined]]> pending - 5 - [5:0] + 7 + [7:0] 0 @@ -563,8 +563,8 @@ console, others undefined]]> enable - 5 - [5:0] + 7 + [7:0] 0 @@ -2315,8 +2315,77 @@ register advances the read pointer automatically.]]> - TICKTIMER + MESSIBLE2 0xF0016000 + MESSIBLE2 + + + IN + + 0x0000 + 0x00 + 32 + read-write + + + in + 7 + [7:0] + 0 + + + + + OUT + + 0x0004 + 0x00 + 32 + read-only + + + out + 7 + [7:0] + 0 + + + + + STATUS + 0x0008 + 0x00 + 32 + read-only + + + full + 0 + [0:0] + 0 + + + + have + 1 + [1:1] + 1 + + + + + + + 0 + 0xc + registers + + + + TICKTIMER + 0xF0017000 TICKTIMER @@ -2374,16 +2443,93 @@ register advances the read pointer automatically.]]> + + MSLEEP_TARGET1 + + 0x000c + 0x00 + 32 + read-write + + + msleep_target + 31 + [31:0] + 0 + + + + + MSLEEP_TARGET0 + + 0x0010 + 0x00 + 32 + read-write + + + msleep_target + 31 + [31:0] + 0 + + + + + EV_STATUS + 0x0014 + 0x00 + 32 + read-write + + + status + 0 + [0:0] + 0 + + + + + EV_PENDING + 0x0018 + 0x00 + 32 + read-write + + + pending + 0 + [0:0] + 0 + + + + + EV_ENABLE + 0x001c + 0x00 + 32 + read-write + + + enable + 0 + [0:0] + 0 + + + 0 - 0xc + 0x20 registers POWER - 0xF0017000 + 0xF0018000 POWER @@ -2542,7 +2688,7 @@ reset fashion]]> SPINOR - 0xF0018000 + 0xF0019000 SPINOR @@ -2617,35 +2763,87 @@ once leads to undefined behavior.]]> - sector_erase + exec_cmd 1 [1:1] 1 - + + + + cmd_code + 9 + [9:2] + 2 + + + + has_arg + 10 + [10:10] + 10 + + + + dummy_cycles + 15 + [15:11] + 11 + 0 implies read]]> + + + data_words + 22 + [22:16] + 16 + + + + lock_reads + 23 + [23:23] + 23 + - SECTOR - + CMD_ARG + 0x0010 0x00 32 read-write - sector + cmd_arg 31 [31:0] 0 - + + + + + + CMD_RBK_DATA + + 0x0014 + 0x00 + 32 + read-only + + + cmd_rbk_data + 31 + [31:0] + 0 + STATUS - 0x0014 + 0x0018 0x00 32 read-only @@ -2659,9 +2857,26 @@ once leads to undefined behavior.]]> + + WDATA + + 0x001c + 0x00 + 32 + read-write + + + wdata + 15 + [15:0] + 0 + + + + EV_STATUS - 0x0018 + 0x0020 0x00 32 read-write @@ -2676,7 +2891,7 @@ once leads to undefined behavior.]]> EV_PENDING - 0x001c + 0x0024 0x00 32 read-write @@ -2691,7 +2906,7 @@ once leads to undefined behavior.]]> EV_ENABLE - 0x0020 + 0x0028 0x00 32 read-write @@ -2706,7 +2921,7 @@ once leads to undefined behavior.]]> ECC_ADDRESS - 0x0024 + 0x002c 0x00 32 read-only @@ -2722,7 +2937,7 @@ once leads to undefined behavior.]]> ECC_STATUS - 0x0028 + 0x0030 0x00 32 read-only @@ -2747,13 +2962,13 @@ checked]]> 0 - 0x2c + 0x34 registers KEYBOARD - 0xF0019000 + 0xF001A000 KEYBOARD @@ -2975,14 +3190,14 @@ again until the interrupt is serviced.]]> SEED - 0xF001A000 + 0xF001B000 SEED SEED1 0x0000 - 0xd261d6d + 0x26732071 32 read-only @@ -2998,7 +3213,7 @@ again until the interrupt is serviced.]]> SEED0 0x0004 - 0x541ad152 + 0x5babc71f 32 read-only @@ -3019,7 +3234,7 @@ again until the interrupt is serviced.]]> ROMTEST - 0xF001B000 + 0xF001C000 ROMTEST @@ -3063,7 +3278,7 @@ again until the interrupt is serviced.]]> AUDIO - 0xF001C000 + 0xF001D000 AUDIO @@ -3205,7 +3420,7 @@ again until the interrupt is serviced.]]> RX_CONF 0x0014 - 0xac4442 + 0xac4441 32 read-only @@ -3334,7 +3549,7 @@ I2S_FORMAT.I2S_STANDARD is I2S standard]]> TX_CONF 0x0020 - 0xac4442 + 0xac4441 32 read-only @@ -3375,7 +3590,7 @@ I2S_FORMAT.I2S_STANDARD is I2S standard]]> TRNG_OSC - 0xF001D000 + 0xF001E000 TRNG_OSC @@ -3464,7 +3679,7 @@ reading the `rand` register]]> AES - 0xF001E000 + 0xF001F000 AES @@ -3948,501 +4163,6 @@ automatically on data and IV ready]]> registers - - SHA2 - 0xF001F000 - SHA2 - - - KEY0 - - 0x0000 - 0x00 - 32 - read-write - - - key0 - 31 - [31:0] - 0 - - - - - KEY1 - - 0x0004 - 0x00 - 32 - read-write - - - key1 - 31 - [31:0] - 0 - - - - - KEY2 - - 0x0008 - 0x00 - 32 - read-write - - - key2 - 31 - [31:0] - 0 - - - - - KEY3 - - 0x000c - 0x00 - 32 - read-write - - - key3 - 31 - [31:0] - 0 - - - - - KEY4 - - 0x0010 - 0x00 - 32 - read-write - - - key4 - 31 - [31:0] - 0 - - - - - KEY5 - - 0x0014 - 0x00 - 32 - read-write - - - key5 - 31 - [31:0] - 0 - - - - - KEY6 - - 0x0018 - 0x00 - 32 - read-write - - - key6 - 31 - [31:0] - 0 - - - - - KEY7 - - 0x001c - 0x00 - 32 - read-write - - - key7 - 31 - [31:0] - 0 - - - - - CONFIG - - 0x0020 - 0x00 - 32 - read-write - - - sha_en - 0 - [0:0] - 0 - - - - endian_swap - 1 - [1:1] - 1 - - - - digest_swap - 2 - [2:2] - 2 - - - - hmac_en - 3 - [3:3] - 3 - - - - - - COMMAND - - 0x0024 - 0x00 - 32 - read-write - - - hash_start - 0 - [0:0] - 0 - - - - hash_process - 1 - [1:1] - 1 - - - - - - WIPE - - 0x0028 - 0x00 - 32 - read-write - - - wipe - 31 - [31:0] - 0 - - - - - DIGEST0 - - 0x002c - 0x00 - 32 - read-only - - - digest0 - 31 - [31:0] - 0 - - - - - DIGEST1 - - 0x0030 - 0x00 - 32 - read-only - - - digest1 - 31 - [31:0] - 0 - - - - - DIGEST2 - - 0x0034 - 0x00 - 32 - read-only - - - digest2 - 31 - [31:0] - 0 - - - - - DIGEST3 - - 0x0038 - 0x00 - 32 - read-only - - - digest3 - 31 - [31:0] - 0 - - - - - DIGEST4 - - 0x003c - 0x00 - 32 - read-only - - - digest4 - 31 - [31:0] - 0 - - - - - DIGEST5 - - 0x0040 - 0x00 - 32 - read-only - - - digest5 - 31 - [31:0] - 0 - - - - - DIGEST6 - - 0x0044 - 0x00 - 32 - read-only - - - digest6 - 31 - [31:0] - 0 - - - - - DIGEST7 - - 0x0048 - 0x00 - 32 - read-only - - - digest7 - 31 - [31:0] - 0 - - - - - MSG_LENGTH1 - - 0x004c - 0x00 - 32 - read-only - - - msg_length - 31 - [31:0] - 0 - - - - - MSG_LENGTH0 - - 0x0050 - 0x00 - 32 - read-only - - - msg_length - 31 - [31:0] - 0 - - - - - ERROR_CODE - - 0x0054 - 0x00 - 32 - read-only - - - error_code - 31 - [31:0] - 0 - - - - - EV_STATUS - 0x0058 - 0x00 - 32 - read-write - - - status - 3 - [3:0] - 0 - - - - - EV_PENDING - 0x005c - 0x00 - 32 - read-write - - - pending - 3 - [3:0] - 0 - - - - - EV_ENABLE - 0x0060 - 0x00 - 32 - read-write - - - enable - 3 - [3:0] - 0 - - - - - FIFO - - 0x0064 - 0x00 - 32 - read-only - - - read_count - 9 - [9:0] - 0 - - - - write_count - 19 - [19:10] - 10 - - - - read_error - 20 - [20:20] - 20 - - - - write_error - 21 - [21:21] - 21 - - - - almost_full - 22 - [22:22] - 22 - - - - almost_empty - 23 - [23:23] - 23 - - - - - - - 0 - 0x68 - registers - - - sha2 - 10 - - SHA512 0xF0020000 @@ -4911,7 +4631,7 @@ in bits]]> sha512 - 11 + 10 @@ -5122,7 +4842,7 @@ exactly reflects the binary layout of an Engine instruction.]]> engine - 12 + 11 @@ -5223,11 +4943,6 @@ exactly reflects the binary layout of an Engine instruction.]]> 0xE0000000 0x00000004 - - SHA2 - 0xE0001000 - 0x00000004 - SHA512 0xE0002000 @@ -5245,4 +4960,4 @@ exactly reflects the binary layout of an Engine instruction.]]> - + \ No newline at end of file