diff --git a/utralib/cramium/daric.svd b/utralib/cramium/daric.svd
index 7c8afa602..032e69c0b 100644
--- a/utralib/cramium/daric.svd
+++ b/utralib/cramium/daric.svd
@@ -1765,8 +1765,8 @@ bit position to clear the flag]]>
sfr_fr
- 1
- [1:0]
+ 2
+ [2:0]
0
@@ -2213,22 +2213,6 @@ position to clear the flag]]>
0x40028000
SCE_GLBSFR
-
- SFR_SCEMODE
-
- 0x0000
- 0x00
- 32
-
-
- cr_scemode
- 1
- [1:0]
- 0
-
-
-
-
SFR_SUBEN
@@ -3547,11 +3531,11 @@ position to clear the flag]]>
32
- sfr_aclkgr
+ aclksubgate
7
[7:0]
0
-
+
@@ -3563,11 +3547,11 @@ position to clear the flag]]>
32
- sfr_hclkgr
+ hclksubgate
7
[7:0]
0
-
+
@@ -3579,11 +3563,11 @@ position to clear the flag]]>
32
- sfr_iclkgr
+ iclksubgate
7
[7:0]
0
-
+
@@ -3595,11 +3579,11 @@ position to clear the flag]]>
32
- sfr_pclkgr
+ pclksubgate
7
[7:0]
0
-
+
@@ -9241,10 +9225,26 @@ respective bit position to clear the flag]]>
+
+ SFR_RAMSEC
+
+ 0x0030
+ 0x00
+ 32
+
+
+ ramsec
+ 3
+ [3:0]
+ 0
+
+
+
+
0
- 0x24
+ 0x34
registers
@@ -10202,14 +10202,14 @@ bit position to clear the flag]]>
GLUECHAIN
- SFR_GCMASK
+ SFR_GCMASK_CR_GCMASK0
0x0000
0x00
32
- cr_gcmask
+ cr_gcmask0
31
[31:0]
0
@@ -10218,14 +10218,14 @@ bit position to clear the flag]]>
- SFR_GCSR
+ SFR_GCSR_GLUEREG0
0x0004
0x00
32
- gluereg
+ gluereg0
31
[31:0]
0
@@ -10234,14 +10234,14 @@ bit position to clear the flag]]>
- SFR_GCRST
+ SFR_GCRST_GLUERST0
0x0008
0x00
32
- gluerst
+ gluerst0
31
[31:0]
0
@@ -10250,14 +10250,14 @@ bit position to clear the flag]]>
- SFR_GCTEST
+ SFR_GCTEST_GLUETEST0
0x000c
0x00
32
- gluetest
+ gluetest0
31
[31:0]
0
@@ -10373,74 +10373,10 @@ bit position to clear the flag]]>
-
- SFR_MLSR_SR_MLSR4
-
- 0x0018
- 0x00
- 32
-
-
- sr_mlsr4
- 31
- [31:0]
- 0
-
-
-
-
-
- SFR_MLSR_SR_MLSR5
-
- 0x001c
- 0x00
- 32
-
-
- sr_mlsr5
- 31
- [31:0]
- 0
-
-
-
-
-
- SFR_MLSR_SR_MLSR6
-
- 0x0020
- 0x00
- 32
-
-
- sr_mlsr6
- 31
- [31:0]
- 0
-
-
-
-
-
- SFR_MLSR_SR_MLSR7
-
- 0x0024
- 0x00
- 32
-
-
- sr_mlsr7
- 31
- [31:0]
- 0
-
-
-
-
0
- 0x28
+ 0x18
registers
@@ -11261,10 +11197,26 @@ bit position to clear the flag]]>
+
+ SFR_AOPADPU
+
+ 0x0064
+ 0x00
+ 32
+
+
+ sfr_aopadpu
+ 9
+ [9:0]
+ 0
+
+
+
+
0
- 0x64
+ 0x68
registers