saymrwulf/xous-core
1
0
Fork 0
mirror of https://github.com/saymrwulf/xous-core.git synced 2026-11-15 08:30:02 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

harmonize register set for testing to what's in hw

Browse source
This commit is contained in:
bunnie 2024-06-21 18:55:54 +08:00
parent 3ae4fde572
commit 3cefb722e6
3 changed files with 15 additions and 15 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
libs/xous-bio/src/bio_tests/i2c.rs
View file

@ -7,9 +7,9 @@ pub fn i2c_test() {
print!("I2C tests\r");
// clear prior test config state
let mut test_cfg = CSR::new(utra::main::HW_MAIN_BASE as *mut u32);
test_cfg.wo(utra::main::WDATA, 0);
test_cfg.wo(utra::main::WDATA, crate::bio_tests::TEST_I2C_MASK);
let mut test_cfg = CSR::new(utra::csrtest::HW_CSRTEST_BASE as *mut u32);
test_cfg.wo(utra::csrtest::WTEST, 0);
test_cfg.wo(utra::csrtest::WTEST, crate::bio_tests::TEST_I2C_MASK);
// setup the machine & test
let mut bio_ss = BioSharedState::new();

4
libs/xous-bio/src/bio_tests/spi.rs
View file

@ -7,8 +7,8 @@ pub fn spi_test() {
print!("SPI test\r");
// clear prior test config state
let mut test_cfg = CSR::new(utra::main::HW_MAIN_BASE as *mut u32);
test_cfg.wo(utra::main::WDATA, 0);
let mut test_cfg = CSR::new(utra::csrtest::HW_CSRTEST_BASE as *mut u32);
test_cfg.wo(utra::csrtest::WTEST, 0);
let mut bio_ss = BioSharedState::new();
// stop all the machines, so that code can be loaded

20
libs/xous-bio/src/bio_tests/units.rs
View file

@ -142,8 +142,8 @@ bio_code!(multiverse_code, MULTIVERSE_START, MULTIVERSE_END,
pub fn fifo_basic() {
print!("FIFO basic\r");
// clear any prior test config state
let mut test_cfg = CSR::new(utra::main::HW_MAIN_BASE as *mut u32);
test_cfg.wo(utra::main::WDATA, 0);
let mut test_cfg = CSR::new(utra::csrtest::HW_CSRTEST_BASE as *mut u32);
test_cfg.wo(utra::csrtest::WTEST, 0);
let mut bio_ss = BioSharedState::new();
// stop all the machines, so that code can be loaded
@ -229,8 +229,8 @@ bio_code!(fifo_basic_code, FIFO_BASIC_START, FIFO_BASIC_END,
pub fn host_fifo_tests() {
print!("Host FIFO tests\r");
// clear prior test config state
let mut test_cfg = CSR::new(utra::main::HW_MAIN_BASE as *mut u32);
test_cfg.wo(utra::main::WDATA, 0);
let mut test_cfg = CSR::new(utra::csrtest::HW_CSRTEST_BASE as *mut u32);
test_cfg.wo(utra::csrtest::WTEST, 0);
let mut bio_ss = BioSharedState::new();
// stop all the machines, so that code can be loaded
@ -248,7 +248,7 @@ pub fn host_fifo_tests() {
bio_ss.bio.wo(utra::bio::SFR_CONFIG, 0);
// invert readbacks via I/O
test_cfg.wo(utra::main::WDATA, TEST_INVERT_MASK);
test_cfg.wo(utra::csrtest::WTEST, TEST_INVERT_MASK);
// start cores 1 & 2
bio_ss.bio.wo(utra::bio::SFR_CTRL, 0x333);
@ -292,7 +292,7 @@ pub fn host_fifo_tests() {
// load next test
// clear inversions, etc on readbacks via I/O
test_cfg.wo(utra::main::WDATA, 0);
test_cfg.wo(utra::csrtest::WTEST, 0);
// stop machine & load code
bio_ss.bio.wo(utra::bio::SFR_CTRL, 0x0);
let code = fifo_host_bitbang_level_trig();
@ -443,8 +443,8 @@ struct FifoLevelTestConfig {
pub fn fifo_level_tests() {
print!("FIFO level comprehensive\r");
// clear prior test config state
let mut test_cfg = CSR::new(utra::main::HW_MAIN_BASE as *mut u32);
test_cfg.wo(utra::main::WDATA, 0);
let mut test_cfg = CSR::new(utra::csrtest::HW_CSRTEST_BASE as *mut u32);
test_cfg.wo(utra::csrtest::WTEST, 0);
let mut bio_ss = BioSharedState::new();
// stop all the machines, so that code can be loaded
@ -703,8 +703,8 @@ pub fn fifo_level_tests() {
pub fn aclk_tests() {
print!("ACLK test\r");
// clear any prior test config state
let mut test_cfg = CSR::new(utra::main::HW_MAIN_BASE as *mut u32);
test_cfg.wo(utra::main::WDATA, 0);
let mut test_cfg = CSR::new(utra::csrtest::HW_CSRTEST_BASE as *mut u32);
test_cfg.wo(utra::csrtest::WTEST, 0);
let mut bio_ss = BioSharedState::new();
// stop all the machines, so that code can be loaded