diff --git a/svd2utra/examples/soc.svd b/svd2utra/examples/soc.svd index 84655cb20..08d3e3f79 100644 --- a/svd2utra/examples/soc.svd +++ b/svd2utra/examples/soc.svd @@ -102,172 +102,9 @@ to the Wishbone/CSR bus are working correctly. The initial reset value of registers - - UART_PHY - 0xF0003000 - UART_PHY - - - TUNING_WORD - 0x0000 - 0x4b7f5a - 32 - read-write - - - tuning_word - 31 - [31:0] - 0 - - - - - - 0 - 0x4 - registers - - - - UART - 0xF0004000 - UART - - - RXTX - 0x0000 - 0x00 - 32 - read-write - - - rxtx - 7 - [7:0] - 0 - - - - - TXFULL - 0x0004 - 0x00 - 32 - read-only - - - txfull - 0 - [0:0] - 0 - - - - - RXEMPTY - 0x0008 - 0x00 - 32 - read-only - - - rxempty - 0 - [0:0] - 0 - - - - - EV_STATUS - 0x000c - 0x00 - 32 - read-write - - - status - 1 - [1:0] - 0 - - - - - EV_PENDING - 0x0010 - 0x00 - 32 - read-write - - - pending - 1 - [1:0] - 0 - - - - - EV_ENABLE - 0x0014 - 0x00 - 32 - read-write - - - enable - 1 - [1:0] - 0 - - - - - TXEMPTY - 0x0018 - 0x00 - 32 - read-only - - - txempty - 0 - [0:0] - 0 - - - - - RXFULL - 0x001c - 0x00 - 32 - read-only - - - rxfull - 0 - [0:0] - 0 - - - - - - 0 - 0x20 - registers - - - uart - 0 - - TIMER0 - 0xF0005000 + 0xF0003000 TIMER0 @@ -407,12 +244,12 @@ the current countdown value to ``value`` register.]]> timer0 - 1 + 0 REBOOT - 0xF0006000 + 0xF0004000 REBOOT @@ -454,7 +291,7 @@ the current countdown value to ``value`` register.]]> CRG - 0xF0007000 + 0xF0005000 CRG @@ -585,8 +422,819 @@ the current countdown value to ``value`` register.]]> - INFO + GPIO + 0xF0006000 + GPIO + + + OUTPUT + + 0x0000 + 0x00 + 32 + read-write + + + output + 5 + [5:0] + 0 + + + + + INPUT + + 0x0004 + 0x00 + 32 + read-only + + + input + 5 + [5:0] + 0 + + + + + DRIVE + + 0x0008 + 0x00 + 32 + read-write + + + drive + 5 + [5:0] + 0 + + + + + INTENA + + 0x000c + 0x00 + 32 + read-only + + + intena + 5 + [5:0] + 0 + + + + + INTPOL + + 0x0010 + 0x00 + 32 + read-only + + + intpol + 5 + [5:0] + 0 + + + + + UARTSEL + + 0x0014 + 0x00 + 32 + read-write + + + uartsel + 1 + [1:0] + 0 + + + + + EV_STATUS + 0x0018 + 0x00 + 32 + read-write + + + status + 5 + [5:0] + 0 + + + + + EV_PENDING + 0x001c + 0x00 + 32 + read-write + + + pending + 5 + [5:0] + 0 + + + + + EV_ENABLE + 0x0020 + 0x00 + 32 + read-write + + + enable + 5 + [5:0] + 0 + + + + + + 0 + 0x24 + registers + + + gpio + 1 + + + + UART_PHY + 0xF0007000 + UART_PHY + + + TUNING_WORD + 0x0000 + 0x4b7f5a + 32 + read-write + + + tuning_word + 31 + [31:0] + 0 + + + + + + 0 + 0x4 + registers + + + + UART 0xF0008000 + UART + + + RXTX + 0x0000 + 0x00 + 32 + read-write + + + rxtx + 7 + [7:0] + 0 + + + + + TXFULL + 0x0004 + 0x00 + 32 + read-only + + + txfull + 0 + [0:0] + 0 + + + + + RXEMPTY + 0x0008 + 0x00 + 32 + read-only + + + rxempty + 0 + [0:0] + 0 + + + + + EV_STATUS + 0x000c + 0x00 + 32 + read-write + + + status + 1 + [1:0] + 0 + + + + + EV_PENDING + 0x0010 + 0x00 + 32 + read-write + + + pending + 1 + [1:0] + 0 + + + + + EV_ENABLE + 0x0014 + 0x00 + 32 + read-write + + + enable + 1 + [1:0] + 0 + + + + + TXEMPTY + 0x0018 + 0x00 + 32 + read-only + + + txempty + 0 + [0:0] + 0 + + + + + RXFULL + 0x001c + 0x00 + 32 + read-only + + + rxfull + 0 + [0:0] + 0 + + + + + + 0 + 0x20 + registers + + + uart + 2 + + + + CONSOLE_PHY + 0xF0009000 + CONSOLE_PHY + + + TUNING_WORD + 0x0000 + 0x4b7f5a + 32 + read-write + + + tuning_word + 31 + [31:0] + 0 + + + + + + 0 + 0x4 + registers + + + + CONSOLE + 0xF000A000 + CONSOLE + + + RXTX + 0x0000 + 0x00 + 32 + read-write + + + rxtx + 7 + [7:0] + 0 + + + + + TXFULL + 0x0004 + 0x00 + 32 + read-only + + + txfull + 0 + [0:0] + 0 + + + + + RXEMPTY + 0x0008 + 0x00 + 32 + read-only + + + rxempty + 0 + [0:0] + 0 + + + + + EV_STATUS + 0x000c + 0x00 + 32 + read-write + + + status + 1 + [1:0] + 0 + + + + + EV_PENDING + 0x0010 + 0x00 + 32 + read-write + + + pending + 1 + [1:0] + 0 + + + + + EV_ENABLE + 0x0014 + 0x00 + 32 + read-write + + + enable + 1 + [1:0] + 0 + + + + + TXEMPTY + 0x0018 + 0x00 + 32 + read-only + + + txempty + 0 + [0:0] + 0 + + + + + RXFULL + 0x001c + 0x00 + 32 + read-only + + + rxfull + 0 + [0:0] + 0 + + + + + + 0 + 0x20 + registers + + + console + 3 + + + + SERVER0_PHY + 0xF000B000 + SERVER0_PHY + + + TUNING_WORD + 0x0000 + 0x4b7f5a + 32 + read-write + + + tuning_word + 31 + [31:0] + 0 + + + + + + 0 + 0x4 + registers + + + + SERVER0 + 0xF000C000 + SERVER0 + + + RXTX + 0x0000 + 0x00 + 32 + read-write + + + rxtx + 7 + [7:0] + 0 + + + + + TXFULL + 0x0004 + 0x00 + 32 + read-only + + + txfull + 0 + [0:0] + 0 + + + + + RXEMPTY + 0x0008 + 0x00 + 32 + read-only + + + rxempty + 0 + [0:0] + 0 + + + + + EV_STATUS + 0x000c + 0x00 + 32 + read-write + + + status + 1 + [1:0] + 0 + + + + + EV_PENDING + 0x0010 + 0x00 + 32 + read-write + + + pending + 1 + [1:0] + 0 + + + + + EV_ENABLE + 0x0014 + 0x00 + 32 + read-write + + + enable + 1 + [1:0] + 0 + + + + + TXEMPTY + 0x0018 + 0x00 + 32 + read-only + + + txempty + 0 + [0:0] + 0 + + + + + RXFULL + 0x001c + 0x00 + 32 + read-only + + + rxfull + 0 + [0:0] + 0 + + + + + + 0 + 0x20 + registers + + + server0 + 4 + + + + SERVER1_PHY + 0xF000D000 + SERVER1_PHY + + + TUNING_WORD + 0x0000 + 0x4b7f5a + 32 + read-write + + + tuning_word + 31 + [31:0] + 0 + + + + + + 0 + 0x4 + registers + + + + SERVER1 + 0xF000E000 + SERVER1 + + + RXTX + 0x0000 + 0x00 + 32 + read-write + + + rxtx + 7 + [7:0] + 0 + + + + + TXFULL + 0x0004 + 0x00 + 32 + read-only + + + txfull + 0 + [0:0] + 0 + + + + + RXEMPTY + 0x0008 + 0x00 + 32 + read-only + + + rxempty + 0 + [0:0] + 0 + + + + + EV_STATUS + 0x000c + 0x00 + 32 + read-write + + + status + 1 + [1:0] + 0 + + + + + EV_PENDING + 0x0010 + 0x00 + 32 + read-write + + + pending + 1 + [1:0] + 0 + + + + + EV_ENABLE + 0x0014 + 0x00 + 32 + read-write + + + enable + 1 + [1:0] + 0 + + + + + TXEMPTY + 0x0018 + 0x00 + 32 + read-only + + + txempty + 0 + [0:0] + 0 + + + + + RXFULL + 0x001c + 0x00 + 32 + read-only + + + rxfull + 0 + [0:0] + 0 + + + + + + 0 + 0x20 + registers + + + server1 + 5 + + + + INFO + 0xF000F000 INFO @@ -1007,7 +1655,7 @@ VCCBRAM (V) = ``Value`` x 3 / 4096.]]> SRAM_EXT - 0xF0009000 + 0xF0010000 SRAM_EXT @@ -1051,7 +1699,7 @@ VCCBRAM (V) = ``Value`` x 3 / 4096.]]> MEMLCD - 0xF000A000 + 0xF0011000 MEMLCD @@ -1164,7 +1812,7 @@ VCCBRAM (V) = ``Value`` x 3 / 4096.]]> COM - 0xF000B000 + 0xF0012000 COM @@ -1285,7 +1933,7 @@ VCCBRAM (V) = ``Value`` x 3 / 4096.]]> I2C - 0xF000C000 + 0xF0013000 I2C @@ -1533,12 +2181,12 @@ upon the completion of one byte of data transfer.]]> i2c - 2 + 6 BTEVENTS - 0xF000D000 + 0xF0014000 BTEVENTS @@ -1594,12 +2242,12 @@ upon the completion of one byte of data transfer.]]> btevents - 3 + 7 MESSIBLE - 0xF000E000 + 0xF0015000 MESSIBLE @@ -1668,7 +2316,7 @@ register advances the read pointer automatically.]]> TICKTIMER - 0xF000F000 + 0xF0016000 TICKTIMER @@ -1735,7 +2383,7 @@ register advances the read pointer automatically.]]> POWER - 0xF0010000 + 0xF0017000 POWER @@ -1894,7 +2542,7 @@ reset fashion]]> SPINOR - 0xF0011000 + 0xF0018000 SPINOR @@ -2105,7 +2753,7 @@ checked]]> KEYBOARD - 0xF0012000 + 0xF0019000 KEYBOARD @@ -2322,161 +2970,19 @@ again until the interrupt is serviced.]]> keyboard - 4 - - - - GPIO - 0xF0013000 - GPIO - - - OUTPUT - - 0x0000 - 0x00 - 32 - read-write - - - output - 5 - [5:0] - 0 - - - - - INPUT - - 0x0004 - 0x00 - 32 - read-only - - - input - 5 - [5:0] - 0 - - - - - DRIVE - - 0x0008 - 0x00 - 32 - read-write - - - drive - 5 - [5:0] - 0 - - - - - INTENA - - 0x000c - 0x00 - 32 - read-only - - - intena - 5 - [5:0] - 0 - - - - - INTPOL - - 0x0010 - 0x00 - 32 - read-only - - - intpol - 5 - [5:0] - 0 - - - - - EV_STATUS - 0x0014 - 0x00 - 32 - read-write - - - status - 5 - [5:0] - 0 - - - - - EV_PENDING - 0x0018 - 0x00 - 32 - read-write - - - pending - 5 - [5:0] - 0 - - - - - EV_ENABLE - 0x001c - 0x00 - 32 - read-write - - - enable - 5 - [5:0] - 0 - - - - - - 0 - 0x20 - registers - - - gpio - 5 + 8 SEED - 0xF0014000 + 0xF001A000 SEED SEED1 0x0000 - 0x64f83336 + 0xd261d6d 32 read-only @@ -2492,7 +2998,7 @@ interrupts.]]> SEED0 0x0004 - 0x60e6ef3 + 0x541ad152 32 read-only @@ -2513,7 +3019,7 @@ interrupts.]]> ROMTEST - 0xF0015000 + 0xF001B000 ROMTEST @@ -2557,7 +3063,7 @@ interrupts.]]> AUDIO - 0xF0016000 + 0xF001C000 AUDIO @@ -2864,12 +3370,12 @@ I2S_FORMAT.I2S_STANDARD is I2S standard]]> audio - 6 + 9 TRNG_OSC - 0xF0017000 + 0xF001D000 TRNG_OSC @@ -2958,7 +3464,7 @@ reading the `rand` register]]> AES - 0xF0018000 + 0xF001E000 AES @@ -3444,7 +3950,7 @@ automatically on data and IV ready]]> SHA2 - 0xF0019000 + 0xF001F000 SHA2 @@ -3934,12 +4440,12 @@ automatically on data and IV ready]]> sha2 - 7 + 10 SHA512 - 0xF001A000 + 0xF0020000 SHA512 @@ -4405,12 +4911,12 @@ in bits]]> sha512 - 8 + 11 ENGINE - 0xF001B000 + 0xF0021000 ENGINE @@ -4616,12 +5122,12 @@ exactly reflects the binary layout of an Engine instruction.]]> engine - 9 + 12 JTAG - 0xF001C000 + 0xF0022000 JTAG