diff --git a/loader/src/platform/cramium/cramium.rs b/loader/src/platform/cramium/cramium.rs
index 46f54c7d6..c31c22ed7 100644
--- a/loader/src/platform/cramium/cramium.rs
+++ b/loader/src/platform/cramium/cramium.rs
@@ -62,6 +62,8 @@ pub fn platform_tests() {
 
 #[cfg(feature="cramium-soc")]
 pub fn early_init() {
+    /*
+    // "actual SoC" parameters
     unsafe {
         (0x400400a0 as *mut u32).write_volatile(0x1F598); // F
         crate::println!("F: {:08x}", ((0x400400a0 as *const u32).read_volatile()));
@@ -93,5 +95,33 @@ pub fn early_init() {
                 crate::println!("{:08x} ok", dat);
             }
         }
+    } */
+    // FPGA board parameters (deals with MMCM instead of PLL)
+    unsafe {
+        let poke_array: [(u32, u32, bool); 9] = [
+            (0x40040030, 0x0001, true),  // cgusel1
+            (0x40040010, 0x0001, true),  // cgusel0
+            (0x40040010, 0x0001, true),  // cgusel0
+            (0x40040014, 0x007f, true),  // fdfclk
+            (0x40040018, 0x007f, true),  // fdaclk
+            (0x4004001c, 0x007f, true),  // fdhclk
+            (0x40040020, 0x007f, true),  // fdiclk
+            (0x40040024, 0x007f, true),  // fdpclk
+            (0x400400a0, 0x4040, false),  // pllmn FPGA
+        ];
+        for &(addr, dat, is_u32) in poke_array.iter() {
+            let rbk = if is_u32 {
+                (addr as *mut u32).write_volatile(dat);
+                (addr as *const u32).read_volatile()
+            } else {
+                (addr as *mut u16).write_volatile(dat as u16);
+                (addr as *const u16).read_volatile() as u32
+            };
+            if dat != rbk {
+                crate::println!("{:08x}(w) != {:08x}(r)", dat, rbk);
+            } else {
+                crate::println!("{:08x} ok", dat);
+            }
+        }
     }
 }
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