uhd/tools
mattprost 9c0dc99e9d tools: update FPGA functional verification tests for X3x0 mcr's & dpdk
-Added test cases for the 184.32MHz clock rate.
-Removed some extra test cases for 200MHz clock rate in order to
cut down on test time.
-Added DPDK test cases (copied from 10gige and 2x_10gige test cases).
2019-11-25 13:38:34 -08:00
..
debs Debian: Minor change to convert_changelog.py 2019-01-09 17:48:13 -08:00
dissectors cmake: Update coding style to use lowercase commands 2018-11-14 14:10:09 -08:00
gr-usrptest tools: update FPGA functional verification tests for X3x0 mcr's & dpdk 2019-11-25 13:38:34 -08:00
kitchen_sink cmake: Use new UHDBoost.cmake in init_usrp and tools 2019-10-15 11:44:38 -07:00
mega_fft MegaFFT: Fixing copyright, whitespace 2015-08-04 15:21:54 -07:00
nirio_programmer cmake: Use new UHDBoost.cmake in init_usrp and tools 2019-10-15 11:44:38 -07:00
uhd_dump uhd_dump: use LIBS instead of LDFLAGS 2014-09-23 13:08:45 -07:00
uhd_txrx_debug_prints debug_prints_tool: Minor cleanup 2014-11-18 13:04:44 +01:00
README.md tools: Added Balints kitchen sink debug util 2014-10-09 19:56:43 +02:00
usrp_x3xx_fpga_jtag_programmer.sh docs: Changed Xilinx ISE version from 14.4 to 14.7 2014-09-24 18:59:01 -07:00

USRP™ Tools

This folder contains tools that are useful for working with and/or debugging your USRP™ device. Tools in this directory are not part of UHD. They are either stand-alone programs or software to be used in third-party applications.

For UHD™ software tools, look in uhd/host/utils.

List of Tools

__chdr-dissector/__

This is a packet dissector for Wireshark. It allows you to view the details of a Compressed HeaDeR (CHDR) formatted-packet in Wireshark. The USRP™ B2xx and X3xx use the CHDR format.

__uhd_dump/__

This tool can be used with tcpdump to make sense of packet dumps from your network-connected USRP™ device.

__usrp_x3xx_fpga_jtag_programmer.sh__

This tool is to be used with the USRP™ X300 and X310 devices. It allows you to program the X3x0 FPGA via JTAG. Note that loading the FPGA image via JTAG does not store the FPGA in the on-device flash storage. Thus, as soon as you cycle power, the image will be lost. To permanently burn an FPGA image, please refer to uhd/host/utils/usrp_x3xx_fpga_burner.

This tool requires that Xilinx iMPACT has been installed on your system.

__kitchen_sink__

This is a debugging tool designed to test and stress connections to USRP devices.