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260 lines
11 KiB
Python
260 lines
11 KiB
Python
#
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# Copyright 2017 Ettus Research (National Instruments)
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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"""
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JESD FPGA Core Interface
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"""
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import time
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from builtins import hex
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from builtins import object
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from .mpmlog import get_logger
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class NIMgJESDCore(object):
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"""
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Provide interface for the FPGA JESD Core.
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Works with Magnesium/Mykonos daughterboards only.
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Arguments:
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regs -- regs class to use for peek/poke
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"""
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DB_ID = 0x0630
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MGT_QPLL_CONTROL = 0x2000
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MGT_PLL_POWER_DOWN_CONTROL = 0x200C
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MGT_TX_RESET_CONTROL = 0x2020
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MGT_RX_RESET_CONTROL = 0x2024
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MGT_RECEIVER_CONTROL = 0x2040
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MGT_RX_DESCRAMBLER_CONTROL = 0x2050
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MGT_TRANSMITTER_CONTROL = 0x2060
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MGT_TX_TRANSCEIVER_CONTROL = 0x2064
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MGT_TX_SCRAMBLER_CONTROL = 0x2068
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LMK_SYNC_CONTROL = 0x206C
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SYSREF_CAPTURE_CONTROL = 0x2078
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JESD_SIGNATURE_REG = 0x2100
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JESD_REVISION_REG = 0x2104
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def __init__(self, regs, slot_idx=0):
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self.regs = regs
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self.log = get_logger("NIMgJESDCore-{}".format(slot_idx))
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assert hasattr(self.regs, 'peek32')
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assert hasattr(self.regs, 'poke32')
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# FutureWork: The following are constants for the Magnesium board. These need
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# to change to variables to support other interfaces.
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self.qplls_used = 1
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self.cplls_used = 0
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# Number of FPGA clock cycles per LMFC period.
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self.lmfc_divider = 20
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def unreset_qpll(self):
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# new_val = self.regs.peek32(0x0) & ~0x8
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# self.log.trace("Unresetting MMCM, writing value {:X}".format(new_val))
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self.regs.poke32(0x0, 0x7)
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def check_core(self):
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"""
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Verify JESD core returns correct ID
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"""
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self.log.trace("Checking JESD Core...")
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if self.regs.peek32(self.JESD_SIGNATURE_REG) != 0x4A455344:
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raise Exception('JESD Core signature mismatch! Check that core is mapped correctly')
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#if self.regs.peek32(JESD_REVISION_REG) != 0xFF
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#error here for date revision mismatch
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self.log.trace("JESD Core build code: {0}".format(hex(self.regs.peek32(self.JESD_REVISION_REG))))
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self.log.trace("DB Slot #: {}".format( (self.regs.peek32(self.DB_ID) & 0x10000) >> 16 ))
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self.log.trace("DB PID: {:X}" .format( self.regs.peek32(self.DB_ID) & 0xFFFF ))
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return True
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def reset(self):
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"""
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Reset to the core. Places the PLLs, TX MGTs and RX MGTs (along with the glue
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logic) in reset. Also disables the SYSREF sampler.
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"""
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self.log.trace("Resetting the JESD204B FPGA core(s)...")
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self._gt_reset('tx', reset_only=True)
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self._gt_reset('rx', reset_only=True)
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self._gt_pll_lock_control(self.qplls_used, self.cplls_used, reset_only=True)
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# Disable SYSREF Sampler
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self.enable_lmfc(False)
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def init_deframer(self):
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" Initialize deframer "
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self.log.trace("Initializing deframer...")
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self.regs.poke32(self.MGT_RECEIVER_CONTROL, 0x2)
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self.regs.poke32(self.MGT_RX_DESCRAMBLER_CONTROL, 0x0)
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self._gt_reset('rx', reset_only=False)
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self.regs.poke32(self.MGT_RECEIVER_CONTROL, 0x0)
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def init_framer(self):
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" Initialize framer "
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self.log.trace("Initializing framer...")
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# Disable DAC Sync from requesting CGS & Stop Deframer
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self.regs.poke32(self.MGT_TRANSMITTER_CONTROL, 0x2002)
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# Reset, unreset, and check the GTs
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self._gt_reset('tx', reset_only=False)
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# MGT phy control... enable TX Driver Swing
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self.regs.poke32(self.MGT_TX_TRANSCEIVER_CONTROL, 0xF0000)
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time.sleep(0.001)
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# Bypass scrambler and disable char replacement
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self.regs.poke32(self.MGT_TX_SCRAMBLER_CONTROL, 0x1)
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# Check for Framer in Idle state
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rb = self.regs.peek32(self.MGT_TRANSMITTER_CONTROL)
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if rb & 0x100 != 0x100:
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raise Exception('TX Framer is not idle after reset')
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# Enable the framer and incoming DAC Sync
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self.regs.poke32(self.MGT_TRANSMITTER_CONTROL, 0x1000)
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self.regs.poke32(self.MGT_TRANSMITTER_CONTROL, 0x0001)
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def get_framer_status(self):
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" Return True if framer is in good status "
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rb = self.regs.peek32(self.MGT_TRANSMITTER_CONTROL)
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self.log.trace("FPGA Framer status: {0}".format(hex(rb & 0xFF0)))
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if rb & (0b1 << 8) == 0b1 << 8:
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self.log.warning("Framer warning: Framer is Idle!")
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elif rb & (0b1 << 6) == 0b0 << 6:
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self.log.warning("Framer warning: Code Group Sync failed to complete!")
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elif rb & (0b1 << 7) == 0b0 << 7:
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self.log.warning("Framer warning: Lane Alignment failed to complete!")
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return rb & 0xFF0 == 0x6C0
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def get_deframer_status(self):
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" Return True if deframer is in good status "
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rb = self.regs.peek32(self.MGT_RECEIVER_CONTROL)
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self.log.trace("FPGA Deframer status: {0}".format(hex(rb & 0xFFFFFFFF)))
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if rb & (0b1 << 2) == 0b0 << 2:
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self.log.warning("Deframer warning: Code Group Sync failed to complete!")
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elif rb & (0b1 << 3) == 0b0 << 3:
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self.log.warning("Deframer warning: Channel Bonding failed to complete!")
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elif rb & (0b1 << 21) == 0b1 << 21:
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self.log.warning("Deframer warning: Misc link error!")
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return rb & 0xFFFFFFFF == 0xF000001C
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def init(self):
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"""
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Initializes the core. Must happen after the reference clock is stable.
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"""
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self.log.trace("Initializing JESD204B FPGA core(s)...")
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self._gt_pll_power_control(self.qplls_used, self.cplls_used)
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self._gt_reset('tx', reset_only=True)
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self._gt_reset('rx', reset_only=True)
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self._gt_pll_lock_control(self.qplls_used, self.cplls_used, reset_only=False)
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# Disable SYSREF Sampler
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self.enable_lmfc(False)
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def enable_lmfc(self, enable=False):
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"""
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Enable/disable LMFC generator in FPGA.
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"""
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disable_bit = 0b1
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if enable:
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disable_bit = 0b0
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reg_val = ((self.lmfc_divider-1) << 23) | (disable_bit << 6)
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self.log.trace("Setting SYSREF Capture reg: 0x{:08X}".format(reg_val))
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self.regs.poke32(self.SYSREF_CAPTURE_CONTROL, reg_val)
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def send_sysref_pulse(self):
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"""
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Toggles the LMK pin that triggers a SYSREF pulse.
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Note: SYSREFs must be enabled on LMK separately beforehand.
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"""
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self.log.trace("Sending SYSREF pulse...")
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self.regs.poke32(self.LMK_SYNC_CONTROL, 0b1 << 30) # Bit 30. Self-clears.
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def _gt_reset(self, tx_or_rx, reset_only=False):
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" Put MGTs into reset. Optionally unresets and enables them "
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assert tx_or_rx.lower() in ('rx', 'tx')
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mgt_reg = {'tx': self.MGT_TX_RESET_CONTROL, 'rx': self.MGT_RX_RESET_CONTROL}[tx_or_rx]
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self.log.trace("Resetting %s MGTs..." % tx_or_rx.upper())
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self.regs.poke32(mgt_reg, 0x10)
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if not reset_only:
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self.regs.poke32(mgt_reg, 0x20)
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rb = -1
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for _ in range(20):
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rb = self.regs.peek32(mgt_reg)
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if rb & 0xFFFF0000 == 0x000F0000:
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return True
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time.sleep(0.001)
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raise Exception('Timeout in GT {trx} Reset (Readback: 0x{rb:X})'.format(
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trx=tx_or_rx.upper(),
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rb=(rb & 0xFFFF0000),
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))
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return True
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def _gt_pll_power_control(self, qplls = 0, cplls = 0):
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" Power down unused CPLLs and QPLLs "
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assert qplls in range(4+1) # valid is 0 - 4
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assert cplls in range(8+1) # valid is 0 - 8
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self.log.trace("Powering down unused CPLLs and QPLLs...")
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self.log.trace("Using {} CPLLs and {} QPLLs!".format(cplls, qplls))
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reg_val = 0xFFFF000F
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reg_val_on = 0x0
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# Power down state is when the corresponding bit is set. For the PLLs we wish to
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# use, clear those bits.
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for x in range(qplls):
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reg_val_on = reg_val_on | 0x1 << x # QPLL bits are 0-3
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for y in range(16, 16 + cplls):
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reg_val_on = reg_val_on | 0x1 << y # CPLL bits are 16-23, others are reserved
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reg_val = reg_val ^ reg_val_on
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self.regs.poke32(self.MGT_PLL_POWER_DOWN_CONTROL, reg_val)
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def _gt_pll_lock_control(self, qplls = 0, cplls = 0, reset_only=False):
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"""
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Turn on the PLLs we're using, and make sure lock bits are set.
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QPLL bitfield mapping: the following nibble is repeated for each QPLL. For
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example, QPLL0 get bits 0-3, QPLL1 get bits 4-7, etc.
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[0] = reset
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[1] = locked
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[2] = unlocked sticky
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[3] = ref clock lost sticky
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...
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[16] = sticky reset (strobe)
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"""
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# FutureWork: CPLLs are NOT supported yet!!!
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assert cplls == 0
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assert qplls in range(4+1) # valid is 0 - 4
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# Reset QPLLs.
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reg_val = 0x1111 # by default assert all resets
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self.regs.poke32(self.MGT_QPLL_CONTROL, reg_val)
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# Unreset the PLLs in use and check for lock.
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if not reset_only:
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if qplls > 0:
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# Unreset only the QPLLs we are using.
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reg_val_on = 0x0
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for nibble in range(qplls):
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reg_val_on = reg_val_on | 0x1 << nibble*4
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reg_val = reg_val ^ reg_val_on
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self.regs.poke32(self.MGT_QPLL_CONTROL, reg_val)
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# Check for lock a short time later.
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time.sleep(0.010)
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# Clear all QPLL sticky bits
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self.regs.poke32(self.MGT_QPLL_CONTROL, 0b1 << 16)
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rb = self.regs.peek32(self.MGT_QPLL_CONTROL)
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self.log.trace("Reading QPLL status register: {:04X}".format(rb & 0xFFFF))
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# Check for lock on active quads only.
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rb_mask = 0x0
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locked_val = 0x0
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for nibble in range(qplls):
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if (rb & (0xF << nibble*4)) != (0x2 << nibble*4):
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self.log.warning("GT QPLL {} failed to lock!".format(nibble))
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locked_val = locked_val | 0x2 << nibble*4
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rb_mask = rb_mask | 0xF << nibble*4
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if (rb & rb_mask) != locked_val:
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raise Exception("One or more GT QPLLs failed to lock!")
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