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380 lines
13 KiB
Python
380 lines
13 KiB
Python
#
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# Copyright 2017 Ettus Research (National Instruments)
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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"""
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N310 implementation module
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"""
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from __future__ import print_function
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import os
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from six import iteritems
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from builtins import object
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from .base import PeriphManagerBase
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from ..net import get_iface_addrs
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from ..net import byte_to_mac
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from ..net import get_mac_addr
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from ..mpmtypes import SID
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from usrp_mpm.uio import UIO
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from ..sysfs_gpio import SysFSGPIO
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from ..ethtable import EthDispatcherTable
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from .. import libpyusrp_periphs as lib
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N3XX_DEFAULT_EXT_CLOCK_FREQ = 10e6
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N3XX_DEFAULT_CLOCK_SOURCE = 'external'
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N3XX_DEFAULT_TIME_SOURCE = 'internal'
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class TCA6424(object):
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"""
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Abstraction layer for the port/gpio expander
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"""
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pins = (
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'PWREN-CLK-MGT156MHz',
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'PWREN-CLK-WB-CDCM',
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'WB-CDCM-RESETn',
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'WB-CDCM-PR0',
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'WB-CDCM-PR1',
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'WB-CDCM-OD0',
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'WB-CDCM-OD1',
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'WB-CDCM-OD2',
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'PWREN-CLK-MAINREF',
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'CLK-MAINREF-SEL1',
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'CLK-MAINREF-SEL0',
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'12',
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'13',
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'FPGA-GPIO-EN',
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'PWREN-CLK-WB-20MHz',
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'PWREN-CLK-WB-25MHz',
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'GPS-PHASELOCK',
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'GPS-nINITSURV',
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'GPS-nRESET',
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'GPS-WARMUP',
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'GPS-SURVEY',
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'GPS-LOCKOK',
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'GPS-ALARM',
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'PWREN-GPS',
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)
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def __init__(self):
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self._gpios = SysFSGPIO('tca6424', 0xFFE7FF, 0x86E7FF)
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def set(self, name, value=None):
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"""
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Assert a pin by name
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"""
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assert name in self.pins
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self._gpios.set(self.pins.index(name), value=value)
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def reset(self, name):
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"""
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Deassert a pin by name
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"""
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self.set(name, value=0)
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def get(self, name):
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"""
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Read back a pin by name
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"""
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assert name in self.pins
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self._gpios.get(self.pins.index(name))
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class FP_GPIO(object):
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"""
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Abstraction layer for the front panel GPIO
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"""
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EMIO_BASE = 54
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FP_GPIO_OFFSET = 32 # Bit offset within the ps_gpio_* pins
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def __init__(self, ddr):
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self._gpiosize = 12
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self._offset = self.FP_GPIO_OFFSET + self.EMIO_BASE
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self.usemask = 0xFFF
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self.ddr = ddr
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self._gpios = SysFSGPIO(
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'zynq_gpio',
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self.usemask<<self._offset,
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self.ddr<<self._offset
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)
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def set_all(self, value):
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"""
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Assert all pin to the value.
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This method will convert value into binary and take the first 6 bits
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assign to 6pins.
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"""
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bin_value = '{0:06b}'.format(value)
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wr_value = bin_value[-(self._gpiosize):]
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for i in range(self._gpiosize):
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if (1<<i)&self.ddr:
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self._gpios.set(self._offset+i, wr_value[i%6])
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def set(self, index, value=None):
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"""
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Assert a pin by index
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"""
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assert index in range(self._gpiosize)
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self._gpios.set(self._offset+index, value)
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def reset_all(self):
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"""
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Deassert all pins
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"""
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for i in range(self._gpiosize):
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self._gpios.reset(self._offset+i)
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def reset(self, index):
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"""
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Deassert a pin by index
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"""
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assert index in range(self._gpiosize)
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self._gpios.reset(self._offset+index)
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def get_all(self):
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"""
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Read back all pins
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"""
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result = 0
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for i in range(self._gpiosize):
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if not (1<<i)&self.ddr:
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value = self._gpios.get(self._offset+i)
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result = (result<<1) | value
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return result
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def get(self, index):
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"""
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Read back a pin by index
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"""
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assert index in range(self._gpiosize)
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return self._gpios.get(self._offset+index)
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class n310(PeriphManagerBase):
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"""
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Holds N310 specific attributes and methods
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"""
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#########################################################################
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# Overridables
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#
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# See PeriphManagerBase for documentation on these fields
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#########################################################################
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pids = [0x4242,]
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mboard_eeprom_addr = "e0005000.i2c"
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mboard_eeprom_max_len = 256
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mboard_info = {"type": "n3xx"}
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dboard_eeprom_addr = "e0004000.i2c"
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dboard_eeprom_max_len = 64
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# We're on a Zynq target, so the following two come from the Zynq standard
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# device tree overlay (tree/arch/arm/boot/dts/zynq-7000.dtsi)
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dboard_spimaster_addrs = ["e0006000.spi", "e0007000.spi"]
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chdr_interfaces = ['eth1', 'eth2']
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# N310-specific settings
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eth_tables = {'eth1': 'misc-enet-regs0', 'eth2': 'misc-enet-regs1'}
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def __init__(self, args):
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# First initialize parent class - will populate self._eeprom_head and self._eeprom_rawdata
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super(n310, self).__init__(args)
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self.log.trace("Initializing TCA6424 port expander controls...")
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self._gpios = TCA6424()
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# Initialize reference clock
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self._gpios.set("PWREN-CLK-MAINREF")
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self._gpios.set("PWREN-CLK-MGT156MHz")
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self._ext_clock_freq = float(
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args.default_args.get('ext_clock_freq', N3XX_DEFAULT_EXT_CLOCK_FREQ)
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)
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self._clock_source = None # Gets set in set_clock_source()
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self.set_clock_source(
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args.default_args.get('clock_source', N3XX_DEFAULT_CLOCK_SOURCE)
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)
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self._time_source = None # Gets set in set_time_source()
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self.set_time_source(
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args.default_args.get(
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'time_source',
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N3XX_DEFAULT_TIME_SOURCE
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)
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)
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self.log.info("mboard info: {}".format(self.mboard_info))
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self._eth_dispatchers = {
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x: EthDispatcherTable(self.eth_tables.get(x))
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for x in list(self._chdr_interfaces.keys())
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}
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for ifname, table in iteritems(self._eth_dispatchers):
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table.set_ipv4_addr(self._chdr_interfaces[ifname]['ip_addr'])
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def init(self, args):
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"""
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Calls init() on the parent class, and then programs the Ethernet
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dispatchers accordingly.
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"""
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result = super(n310, self).init(args)
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for _, table in iteritems(self._eth_dispatchers):
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if 'forward_eth' in args or 'forward_bcast' in args:
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table.set_forward_policy(
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args.get('forward_eth', False),
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args.get('forward_bcast', False)
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)
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if 'preload_ethtables' in args:
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self._preload_ethtables(
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self._eth_dispatchers,
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args['preload_ethtables']
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)
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return result
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def _preload_ethtables(self, eth_dispatchers, table_file):
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"""
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Populates the ethernet tables from a JSON file
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"""
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import json
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try:
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eth_table_data = json.load(open(table_file))
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except ValueError as ex:
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self.log.warning(
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"Bad values in preloading table file: %s",
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str(ex)
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)
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return
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self.log.info(
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"Preloading Ethernet dispatch tables from JSON file `%s'.",
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table_file
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)
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for eth_iface, data in iteritems(eth_table_data):
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if eth_iface not in eth_dispatchers:
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self.log.warning(
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"Request to preload eth dispatcher table for "
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"iface `{}', but no such interface is "
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"registered. Known interfaces: {}".format(
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str(eth_iface),
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",".join(eth_dispatchers.keys())
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)
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)
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continue
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eth_dispatcher = eth_dispatchers[eth_iface]
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self.log.debug("Preloading {} dispatch table".format(eth_iface))
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try:
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for dst_ep, udp_data in iteritems(data):
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sid = SID()
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sid.set_dst_ep(int(dst_ep))
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eth_dispatcher.set_route(
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sid,
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udp_data['ip_addr'],
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udp_data['port'],
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udp_data.get('mac_addr', None)
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)
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except ValueError as ex:
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self.log.warning(
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"Bad values in preloading table file: %s",
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str(ex)
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)
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def _allocate_sid(self, sender_addr, port, sid, xbar_src_addr, xbar_src_port, new_ep):
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"""
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Get the MAC address of the sender and store it in the FPGA ARP table
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"""
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mac_addr = get_mac_addr(sender_addr)
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if new_ep not in self._available_endpoints:
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raise RuntimeError("no more sids yo")
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self._available_endpoints.remove(new_ep)
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if mac_addr is not None:
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if sender_addr not in self.sid_endpoints:
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self.sid_endpoints.update({sender_addr: (new_ep,)})
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else:
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current_allocation = self.sid_endpoints.get(sender_addr)
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new_allocation = current_allocation + (new_ep,)
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self.sid_endpoints.update({sender_addr: new_allocation})
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sid = SID(sid)
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sid.set_src_addr(xbar_src_addr)
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sid.set_src_ep(new_ep)
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my_xbar = lib.xbar.xbar.make("/dev/crossbar0") # TODO
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my_xbar.set_route(xbar_src_addr, 0) # TODO
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eth_dispatcher = self._eth_dispatchers['eth1'] # TODO
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eth_dispatcher.set_route(sid.reversed(), sender_addr, port)
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return sid.get()
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def get_clock_sources(self):
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" Lists all available clock sources. "
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self.log.trace("Listing available clock sources...")
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return ('external', 'internal', 'gpsdo')
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def get_clock_source(self):
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" Returns the currently selected clock source "
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return self._clock_source
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def set_clock_source(self, *args):
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"""
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Enable given external reference clock.
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Throws if clock_source is not a valid value.
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"""
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clock_source = args[0]
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assert clock_source in self.get_clock_sources()
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self.log.trace("Setting clock source to `{}'".format(clock_source))
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if clock_source == 'internal':
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self._gpios.set("CLK-MAINREF-SEL0")
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self._gpios.set("CLK-MAINREF-SEL1")
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elif clock_source == 'gpsdo':
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self._gpios.set("CLK-MAINREF-SEL0")
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self._gpios.reset("CLK-MAINREF-SEL1")
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else: # external
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self._gpios.reset("CLK-MAINREF-SEL0")
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self._gpios.reset("CLK-MAINREF-SEL1")
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self._clock_source = clock_source
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ref_clk_freq = self.get_ref_clock_freq()
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for slot, dboard in enumerate(self.dboards):
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if hasattr(dboard, 'update_ref_clock_freq'):
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self.log.trace(
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"Updating reference clock on dboard `{}' to {} MHz...".format(
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slot, ref_clk_freq/1e6
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)
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)
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dboard.update_ref_clock_freq(ref_clk_freq)
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def set_ref_clock_freq(self, freq):
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"""
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Tell our USRP what the frequency of the external reference clock is.
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Will throw if it's not a valid value.
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"""
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assert freq in (10e6, 20e6, 25e6)
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self._ext_clock_freq = freq
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def get_ref_clock_freq(self):
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" Returns the currently active reference clock frequency"
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return {
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'internal': 25e6,
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'external': self._ext_clock_freq,
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'gpsdo': 20e6,
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}[self._clock_source]
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def get_time_sources(self):
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" Returns list of valid time sources "
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return ['internal', 'external']
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def get_time_source(self):
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" Return the currently selected time source "
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return self._time_source
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def set_time_source(self, time_source):
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" Set a time source "
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assert time_source in self.get_time_sources()
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self.log.trace("Setting time source to `{}'".format(time_source))
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# FIXME use uio
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if time_source == 'internal':
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os.system('devmem2 0x4001000C w 0x1')
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elif time_source == 'external':
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os.system('devmem2 0x4001000C w 0x0')
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else:
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assert False
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