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bfff8b79b9
This commit adds daughterboard simulation to the simulator. There is a sim_dboard class which registers it's methods with the rpc server. These methods are visible over mpm as well as the mpm_shell. Signed-off-by: Samuel O'Brien <sam.obrien@ni.com>
33 lines
943 B
Python
33 lines
943 B
Python
#
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# Copyright 2020 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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from .sim_dboard import SimulatedDboardBase
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class SimulatedCatalinaDboard(SimulatedDboardBase):
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pids = [0x0110]
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extra_methods = [
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("set_gain", lambda target, gain: gain),
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("catalina_tune", lambda which, freq: freq),
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("set_bw_filter", lambda which, freq: freq),
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"set_dc_offset_auto",
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"set_iq_balance_auto",
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"set_agc",
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"set_active_chains",
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"set_timing_mode",
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"data_port_loopback"
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]
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def __init__(self, slot_idx, clock_rate_cb, **kwargs):
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super().__init__(slot_idx, **kwargs)
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self.clock_rate_cb = clock_rate_cb
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self.master_clock_rate = 122.88e6
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def get_master_clock_rate(self):
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return self.master_clock_rate
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def set_catalina_clock_rate(self, rate):
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self.clock_rate_cb(rate)
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return rate
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