mirror of
https://github.com/saymrwulf/uhd.git
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7e1b567d53
Blocks that change scaling, tick rate, or sampling rate can now notify the graph to update streamers. Before, this was handled only by mult_usrp, and only for DDC and DUC blocks.
313 lines
13 KiB
C++
313 lines
13 KiB
C++
//
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// Copyright 2016-2018 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: GPL-3.0-or-later
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//
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#include <uhd/convert.hpp>
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#include <uhd/rfnoc/duc_block_ctrl.hpp>
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#include <uhd/types/ranges.hpp>
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#include <uhd/utils/log.hpp>
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#include <uhdlib/usrp/cores/dsp_core_utils.hpp>
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#include <uhdlib/utils/compat_check.hpp>
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#include <uhdlib/utils/math.hpp>
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#include <uhdlib/utils/narrow.hpp>
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#include <boost/math/special_functions/round.hpp>
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#include <cmath>
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using namespace uhd::rfnoc;
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class duc_block_ctrl_impl : public duc_block_ctrl
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{
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public:
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UHD_RFNOC_BLOCK_CONSTRUCTOR(duc_block_ctrl)
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, _fpga_compat(user_reg_read64(RB_REG_COMPAT_NUM)),
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_num_halfbands(uhd::narrow_cast<size_t>(user_reg_read64(RB_REG_NUM_HALFBANDS))),
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_cic_max_interp(uhd::narrow_cast<size_t>(user_reg_read64(RB_REG_CIC_MAX_INTERP)))
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{
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UHD_LOG_DEBUG(unique_id(),
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"Loading DUC with " << get_num_halfbands()
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<< " halfbands and "
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"max CIC interpolation "
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<< get_cic_max_interp());
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uhd::assert_fpga_compat(MAJOR_COMP,
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MINOR_COMP,
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_fpga_compat,
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"DUC",
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"DUC",
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false /* Let it slide if minors mismatch */
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);
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// Argument/prop tree hooks
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for (size_t chan = 0; chan < get_input_ports().size(); chan++) {
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const double default_freq = get_arg<double>("freq", chan);
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_tree->access<double>(get_arg_path("freq/value", chan))
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.set_coercer([this, chan](const double value) {
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return this->set_freq(value, chan);
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})
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.set(default_freq);
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;
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const double default_input_rate = get_arg<double>("input_rate", chan);
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_tree->access<double>(get_arg_path("input_rate/value", chan))
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.set_coercer([this, chan](const double value) {
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return this->set_input_rate(value, chan);
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})
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.set(default_input_rate)
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.add_coerced_subscriber([this](const double) { update_graph(); });
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_tree->access<double>(get_arg_path("output_rate/value", chan))
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.add_coerced_subscriber([this, chan](const double rate) {
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this->set_output_rate(rate, chan);
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})
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.add_coerced_subscriber([this](const double) { update_graph(); });
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// Legacy properties (for backward compat w/ multi_usrp)
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const uhd::fs_path dsp_base_path = _root_path / "legacy_api" / chan;
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// Legacy properties
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_tree->create<double>(dsp_base_path / "rate/value")
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.set_coercer([this, chan](const double value) {
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return this->_tree
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->access<double>(this->get_arg_path("input_rate/value", chan))
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.set(value)
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.get();
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})
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.set_publisher([this, chan]() {
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return this->_tree
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->access<double>(this->get_arg_path("input_rate/value", chan))
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.get();
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});
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_tree->create<uhd::meta_range_t>(dsp_base_path / "rate/range")
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.set_publisher([this]() { return get_input_rates(); });
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_tree->create<double>(dsp_base_path / "freq/value")
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.set_coercer([this, chan](const double value) {
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return this->_tree
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->access<double>(this->get_arg_path("freq/value", chan))
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.set(value)
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.get();
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})
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.set_publisher([this, chan]() {
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return this->_tree
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->access<double>(this->get_arg_path("freq/value", chan))
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.get();
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});
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_tree->create<uhd::meta_range_t>(dsp_base_path / "freq/range")
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.set_publisher([this]() { return get_freq_range(); });
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_tree->access<uhd::time_spec_t>("time/cmd")
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.add_coerced_subscriber([this, chan](const uhd::time_spec_t time_spec) {
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this->set_command_time(time_spec, chan);
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});
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if (_tree->exists("tick_rate")) {
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const double tick_rate = _tree->access<double>("tick_rate").get();
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set_command_tick_rate(tick_rate, chan);
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_tree->access<double>("tick_rate")
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.add_coerced_subscriber([this, chan](const double rate) {
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this->set_command_tick_rate(rate, chan);
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});
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}
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// Rate 1:1 by default
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sr_write("N", 1, chan);
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sr_write("M", 1, chan);
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sr_write("CONFIG", 1, chan); // Enable clear EOB
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}
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} // end ctor
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virtual ~duc_block_ctrl_impl() {}
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double get_input_scale_factor(size_t port = ANY_PORT)
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{
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port = (port == ANY_PORT) ? 0 : port;
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if (not(_tx_streamer_active.count(port) and _tx_streamer_active.at(port))) {
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return SCALE_UNDEFINED;
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}
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return get_arg<double>("scalar_correction", port);
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}
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double get_input_samp_rate(size_t port = ANY_PORT)
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{
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port = (port == ANY_PORT) ? 0 : port;
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// Wait, what? If this seems out of place to you, you're right. However,
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// we need a function call that is called when the graph is complete,
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// but streaming is not yet set up.
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if (_tree->exists("tick_rate")) {
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const double tick_rate = _tree->access<double>("tick_rate").get();
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set_command_tick_rate(tick_rate, port);
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}
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if (not(_tx_streamer_active.count(port) and _tx_streamer_active.at(port))) {
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return RATE_UNDEFINED;
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}
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return get_arg<double>("input_rate", port);
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}
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double get_output_samp_rate(size_t port = ANY_PORT)
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{
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port = (port == ANY_PORT) ? 0 : port;
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if (not(_tx_streamer_active.count(port) and _tx_streamer_active.at(port))) {
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return RATE_UNDEFINED;
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}
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return get_arg<double>("output_rate", port == ANY_PORT ? 0 : port);
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}
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void issue_stream_cmd(const uhd::stream_cmd_t& stream_cmd_, const size_t chan)
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{
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UHD_RFNOC_BLOCK_TRACE() << "duc_block_ctrl_base::issue_stream_cmd()";
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uhd::stream_cmd_t stream_cmd = stream_cmd_;
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if (stream_cmd.stream_mode == uhd::stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_DONE
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or stream_cmd.stream_mode
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== uhd::stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_MORE) {
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size_t interpolation = get_arg<double>("output_rate", chan)
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/ get_arg<double>("input_rate", chan);
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stream_cmd.num_samps *= interpolation;
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}
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source_block_ctrl_base::issue_stream_cmd(stream_cmd, chan);
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}
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private:
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static constexpr size_t MAJOR_COMP = 2;
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static constexpr size_t MINOR_COMP = 0;
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static constexpr size_t RB_REG_COMPAT_NUM = 0;
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static constexpr size_t RB_REG_NUM_HALFBANDS = 1;
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static constexpr size_t RB_REG_CIC_MAX_INTERP = 2;
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const uint64_t _fpga_compat;
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const size_t _num_halfbands;
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const size_t _cic_max_interp;
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//! Set the DDS frequency shift the signal to \p requested_freq
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double set_freq(const double requested_freq, const size_t chan)
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{
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const double output_rate = get_arg<double>("output_rate");
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double actual_freq;
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int32_t freq_word;
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get_freq_and_freq_word(requested_freq, output_rate, actual_freq, freq_word);
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sr_write("DDS_FREQ", uint32_t(freq_word), chan);
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return actual_freq;
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}
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//! Return a range of valid frequencies the DDS can tune to
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uhd::meta_range_t get_freq_range(void)
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{
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const double output_rate = get_arg<double>("output_rate");
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return uhd::meta_range_t(
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-output_rate / 2, +output_rate / 2, output_rate / std::pow(2.0, 32));
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}
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uhd::meta_range_t get_input_rates(void)
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{
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uhd::meta_range_t range;
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const double output_rate = get_arg<double>("output_rate");
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for (int hb = _num_halfbands; hb >= 0; hb--) {
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const size_t interp_offset = _cic_max_interp << (hb - 1);
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for (size_t interp = _cic_max_interp; interp > 0; interp--) {
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const size_t hb_cic_interp = interp * (1 << hb);
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if (hb == 0 || hb_cic_interp > interp_offset) {
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range.push_back(uhd::range_t(output_rate / hb_cic_interp));
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}
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}
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}
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return range;
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}
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double set_input_rate(const double requested_rate, const size_t chan)
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{
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const double output_rate = get_arg<double>("output_rate", chan);
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const double tick_rate = _tree->exists("tick_rate")
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? _tree->access<double>("tick_rate").get()
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: output_rate;
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const size_t n = size_t(tick_rate / output_rate);
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const size_t interp_rate = boost::math::iround(
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output_rate / get_input_rates().clip(requested_rate, true));
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size_t interp = interp_rate;
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uint32_t hb_enable = 0;
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while ((interp % 2 == 0) and hb_enable < _num_halfbands) {
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hb_enable++;
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interp /= 2;
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}
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UHD_ASSERT_THROW(hb_enable <= _num_halfbands);
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UHD_ASSERT_THROW(interp > 0 and interp <= _cic_max_interp);
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// What we can't cover with halfbands, we do with the CIC
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sr_write("INTERP_WORD", (hb_enable << 8) | (interp & 0xff), chan);
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// Rate change = M/N
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sr_write("N", n, chan);
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sr_write("M", n * std::pow(2.0, double(hb_enable)) * (interp & 0xff), chan);
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if (interp > 1 and hb_enable == 0) {
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UHD_LOGGER_WARNING("RFNOC")
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<< boost::format(
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"The requested interpolation is odd; the user should expect "
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"passband CIC rolloff.\n"
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"Select an even interpolation to ensure that a halfband filter is "
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"enabled.\n"
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"interpolation = dsp_rate/samp_rate -> %d = (%f MHz)/(%f MHz)\n")
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% interp_rate % (output_rate / 1e6) % (requested_rate / 1e6);
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}
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// Calculate algorithmic gain of CIC for a given interpolation
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// For Ettus CIC R=interp, M=1, N=4. Gain = (R * M) ^ (N - 1)
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const int CIC_N = 4;
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const double rate_pow = std::pow(double(interp & 0xff), CIC_N - 1);
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const double CONSTANT_GAIN = 1.0;
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const double scaling_adjustment =
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std::pow(2, uhd::math::ceil_log2(rate_pow)) / (CONSTANT_GAIN * rate_pow);
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update_scalar(scaling_adjustment, chan);
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return output_rate / interp_rate;
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}
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//! Set frequency and interpolation again
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void set_output_rate(const double /* rate */, const size_t chan)
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{
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const double desired_freq =
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_tree->access<double>(get_arg_path("freq", chan) / "value").get_desired();
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set_arg<double>("freq", desired_freq, chan);
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const double desired_input_rate =
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_tree->access<double>(get_arg_path("input_rate", chan) / "value")
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.get_desired();
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set_arg<double>("input_rate", desired_input_rate, chan);
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}
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// Calculate compensation gain values for algorithmic gain of DDS and CIC taking into
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// account gain compensation blocks already hardcoded in place in DUC (that provide
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// simple 1/2^n gain compensation). Further more factor in OTW format which adds
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// further gain factor to weight output samples correctly.
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void update_scalar(const double scalar, const size_t chan)
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{
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const double target_scalar = (1 << 15) * scalar;
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const int32_t actual_scalar = boost::math::iround(target_scalar);
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// Calculate the error introduced by using integer representation for the scalar
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const double scalar_correction =
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actual_scalar / target_scalar
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* (double(1 << 15) - 1.0) // Rounding error, normalized to 1.0
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* get_arg<double>("fullscale"); // Scaling requested by host
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set_arg<double>("scalar_correction", scalar_correction, chan);
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// Write DUC with scaling correction for CIC and CORDIC that maximizes dynamic
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// range in 32/16/12/8bits.
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sr_write("SCALE_IQ", actual_scalar, chan);
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}
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//! Get cached value of FPGA compat number
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uint64_t get_fpga_compat() const
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{
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return _fpga_compat;
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}
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// Get cached value of _num_halfbands
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size_t get_num_halfbands() const
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{
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return _num_halfbands;
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}
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// Get cached value of _cic_max_decim readback
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size_t get_cic_max_interp() const
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{
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return _cic_max_interp;
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}
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};
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UHD_RFNOC_BLOCK_REGISTER(duc_block_ctrl, "DUC");
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