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https://github.com/saymrwulf/uhd.git
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7b9a7e74dc
When an ICMP dest unreachable pkt arrives, the fw needs to know how to shutoff the DSP. This offset for the reset register was broken by a previous fix for register overlap.
162 lines
4.7 KiB
C
162 lines
4.7 KiB
C
//
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// Copyright 2010-2012 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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#ifndef INCLUDED_USRP2_FW_COMMON_H
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#define INCLUDED_USRP2_FW_COMMON_H
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#include <stdint.h>
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/*!
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* Structs and constants for usrp2 communication.
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* This header is shared by the firmware and host code.
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* Therefore, this header may only contain valid C code.
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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//fpga and firmware compatibility numbers
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#define USRP2_FPGA_COMPAT_NUM 10
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#define USRP2_FW_COMPAT_NUM 12
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#define USRP2_FW_VER_MINOR 4
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//used to differentiate control packets over data port
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#define USRP2_INVALID_VRT_HEADER 0
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typedef struct{
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uint32_t sequence;
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uint32_t vrt_hdr;
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uint32_t ip_addr;
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uint32_t udp_port;
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} usrp2_stream_ctrl_t;
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// udp ports for the usrp2 communication
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// Dynamic and/or private ports: 49152-65535
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#define USRP2_UDP_CTRL_PORT 49152
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//#define USRP2_UDP_UPDATE_PORT 49154
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#define USRP2_UDP_RX_DSP0_PORT 49156
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#define USRP2_UDP_TX_DSP0_PORT 49157
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#define USRP2_UDP_RX_DSP1_PORT 49158
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#define USRP2_UDP_FIFO_CRTL_PORT 49159
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#define USRP2_UDP_UART_BASE_PORT 49170
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#define USRP2_UDP_UART_GPS_PORT 49172
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// Map for virtual firmware regs (not very big so we can keep it here for now)
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#define U2_FW_REG_LOCK_TIME 0
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#define U2_FW_REG_LOCK_GPID 1
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#define U2_FW_REG_HAS_GPSDO 3
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#define U2_FW_REG_VER_MINOR 7
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////////////////////////////////////////////////////////////////////////
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// I2C addresses
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////////////////////////////////////////////////////////////////////////
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#define USRP2_I2C_DEV_EEPROM 0x50 // 24LC02[45]: 7-bits 1010xxx
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#define USRP2_I2C_ADDR_MBOARD (USRP2_I2C_DEV_EEPROM | 0x0)
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#define USRP2_I2C_ADDR_TX_DB (USRP2_I2C_DEV_EEPROM | 0x4)
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#define USRP2_I2C_ADDR_RX_DB (USRP2_I2C_DEV_EEPROM | 0x5)
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////////////////////////////////////////////////////////////////////////
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// EEPROM Layout
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////////////////////////////////////////////////////////////////////////
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#define USRP2_EE_MBOARD_REV 0x00 //2 bytes, little-endian (historic, don't blame me)
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#define USRP2_EE_MBOARD_MAC_ADDR 0x02 //6 bytes
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#define USRP2_EE_MBOARD_GATEWAY 0x38 //uint32, big-endian
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#define USRP2_EE_MBOARD_SUBNET 0x08 //uint32, big-endian
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#define USRP2_EE_MBOARD_IP_ADDR 0x0C //uint32, big-endian
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#define USRP2_EE_MBOARD_BOOTLOADER_FLAGS 0xF7
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typedef enum{
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USRP2_CTRL_ID_HUH_WHAT = ' ',
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//USRP2_CTRL_ID_FOR_SURE, //TODO error condition enums
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//USRP2_CTRL_ID_SUX_MAN,
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USRP2_CTRL_ID_WAZZUP_BRO = 'a',
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USRP2_CTRL_ID_WAZZUP_DUDE = 'A',
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USRP2_CTRL_ID_TRANSACT_ME_SOME_SPI_BRO = 's',
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USRP2_CTRL_ID_OMG_TRANSACTED_SPI_DUDE = 'S',
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USRP2_CTRL_ID_DO_AN_I2C_READ_FOR_ME_BRO = 'i',
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USRP2_CTRL_ID_HERES_THE_I2C_DATA_DUDE = 'I',
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USRP2_CTRL_ID_WRITE_THESE_I2C_VALUES_BRO = 'h',
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USRP2_CTRL_ID_COOL_IM_DONE_I2C_WRITE_DUDE = 'H',
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USRP2_CTRL_ID_GET_THIS_REGISTER_FOR_ME_BRO = 'r',
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USRP2_CTRL_ID_OMG_GOT_REGISTER_SO_BAD_DUDE = 'R',
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USRP2_CTRL_ID_HOLLER_AT_ME_BRO = 'l',
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USRP2_CTRL_ID_HOLLER_BACK_DUDE = 'L',
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USRP2_CTRL_ID_PEACE_OUT = '~'
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} usrp2_ctrl_id_t;
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typedef enum{
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USRP2_DIR_RX = 'r',
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USRP2_DIR_TX = 't'
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} usrp2_dir_which_t;
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typedef enum{
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USRP2_CLK_EDGE_RISE = 'r',
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USRP2_CLK_EDGE_FALL = 'f'
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} usrp2_clk_edge_t;
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typedef enum{
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USRP2_REG_ACTION_FPGA_PEEK32 = 1,
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USRP2_REG_ACTION_FPGA_PEEK16 = 2,
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USRP2_REG_ACTION_FPGA_POKE32 = 3,
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USRP2_REG_ACTION_FPGA_POKE16 = 4,
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USRP2_REG_ACTION_FW_PEEK32 = 5,
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USRP2_REG_ACTION_FW_POKE32 = 6
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} usrp2_reg_action_t;
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typedef struct{
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uint32_t proto_ver;
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uint32_t id;
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uint32_t seq;
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union{
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uint32_t ip_addr;
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struct {
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uint32_t dev;
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uint32_t data;
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uint8_t miso_edge;
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uint8_t mosi_edge;
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uint8_t num_bits;
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uint8_t readback;
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} spi_args;
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struct {
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uint8_t addr;
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uint8_t bytes;
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uint8_t data[20];
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} i2c_args;
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struct {
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uint32_t addr;
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uint32_t data;
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uint8_t action;
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} reg_args;
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struct {
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uint32_t len;
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} echo_args;
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} data;
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} usrp2_ctrl_data_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* INCLUDED_USRP2_FW_COMMON_H */
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