mirror of
https://github.com/saymrwulf/uhd.git
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228 lines
8.6 KiB
C++
228 lines
8.6 KiB
C++
//
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// Copyright 2011-2014 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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#include "max2870_regs.hpp"
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#include "db_sbx_common.hpp"
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#include <boost/algorithm/string.hpp>
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using namespace uhd;
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using namespace uhd::usrp;
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using namespace boost::assign;
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/***********************************************************************
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* Structors
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**********************************************************************/
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sbx_xcvr::cbx::cbx(sbx_xcvr *_self_sbx_xcvr) {
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//register the handle to our base CBX class
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self_base = _self_sbx_xcvr;
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}
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sbx_xcvr::cbx::~cbx(void){
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/* NOP */
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}
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/***********************************************************************
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* Tuning
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**********************************************************************/
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double sbx_xcvr::cbx::set_lo_freq(dboard_iface::unit_t unit, double target_freq) {
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UHD_LOGV(often) << boost::format(
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"CBX tune: target frequency %f Mhz"
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) % (target_freq/1e6) << std::endl;
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/*
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* If the user sets 'mode_n=integer' in the tuning args, the user wishes to
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* tune in Integer-N mode, which can result in better spur
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* performance on some mixers. The default is fractional tuning.
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*/
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property_tree::sptr subtree = (unit == dboard_iface::UNIT_RX) ? self_base->get_rx_subtree()
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: self_base->get_tx_subtree();
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device_addr_t tune_args = subtree->access<device_addr_t>("tune_args").get();
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bool is_int_n = boost::iequals(tune_args.get("mode_n",""), "integer");
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//clip the input
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target_freq = cbx_freq_range.clip(target_freq);
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//map mode setting to valid integer divider (N) values
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static const uhd::range_t int_n_mode_div_range(16,4095,1);
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static const uhd::range_t frac_n_mode_div_range(19,4091,1);
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//map rf divider select output dividers to enums
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static const uhd::dict<int, max2870_regs_t::rf_divider_select_t> rfdivsel_to_enum = map_list_of
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(1, max2870_regs_t::RF_DIVIDER_SELECT_DIV1)
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(2, max2870_regs_t::RF_DIVIDER_SELECT_DIV2)
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(4, max2870_regs_t::RF_DIVIDER_SELECT_DIV4)
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(8, max2870_regs_t::RF_DIVIDER_SELECT_DIV8)
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(16, max2870_regs_t::RF_DIVIDER_SELECT_DIV16)
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(32, max2870_regs_t::RF_DIVIDER_SELECT_DIV32)
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(64, max2870_regs_t::RF_DIVIDER_SELECT_DIV64)
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(128, max2870_regs_t::RF_DIVIDER_SELECT_DIV128)
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;
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double actual_freq, pfd_freq;
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double ref_freq = self_base->get_iface()->get_clock_rate(unit);
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int R=0, BS=0, N=0, FRAC=0, MOD=4095;
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int RFdiv = 1;
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max2870_regs_t::reference_divide_by_2_t T = max2870_regs_t::REFERENCE_DIVIDE_BY_2_DISABLED;
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max2870_regs_t::reference_doubler_t D = max2870_regs_t::REFERENCE_DOUBLER_DISABLED;
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//Reference doubler for 50% duty cycle
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// if ref_freq < 12.5MHz enable regs.reference_divide_by_2
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//NOTE: MAX2870 goes down to 10MHz ref vs. 12.5MHz on ADF4351
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if(ref_freq <= 10.0e6) D = max2870_regs_t::REFERENCE_DOUBLER_ENABLED;
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//increase RF divider until acceptable VCO frequency
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double vco_freq = target_freq;
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//NOTE: MIN freq for MAX2870 VCO is 3GHz vs. 2.2GHz on ADF4351
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while (vco_freq < 3e9) {
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vco_freq *= 2;
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RFdiv *= 2;
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}
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/*
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* The goal here is to loop though possible R dividers,
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* band select clock dividers, N (int) dividers, and FRAC
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* (frac) dividers.
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*
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* Calculate the N and F dividers for each set of values.
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* The loop exits when it meets all of the constraints.
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* The resulting loop values are loaded into the registers.
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*
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* from pg.21
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*
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* f_pfd = f_ref*(1+D)/(R*(1+T))
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* f_vco = (N + (FRAC/MOD))*f_pfd
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* N = f_vco/f_pfd - FRAC/MOD = f_vco*((R*(T+1))/(f_ref*(1+D))) - FRAC/MOD
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* f_rf = f_vco/RFdiv
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*/
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for(R = 1; R <= 1023; R+=1){
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//PFD input frequency = f_ref/R ... ignoring Reference doubler/divide-by-2 (D & T)
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pfd_freq = ref_freq*(1+D)/(R*(1+T));
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//keep the PFD frequency at or below 25MHz
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if (pfd_freq > 25e6) continue;
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//ignore fractional part of tuning
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N = int(vco_freq/pfd_freq);
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//Fractional-N calculation
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FRAC = int((vco_freq/pfd_freq - N)*MOD);
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if(is_int_n) {
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if (FRAC > (MOD / 2)) { //Round integer such that actual freq is closest to target
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N++;
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}
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FRAC = 0;
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}
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//keep N within int divider requirements
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if(is_int_n) {
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if(N < int_n_mode_div_range.start()) continue;
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if(N > int_n_mode_div_range.stop()) continue;
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} else {
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if(N < frac_n_mode_div_range.start()) continue;
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if(N > frac_n_mode_div_range.stop()) continue;
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}
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//keep pfd freq low enough to achieve 50kHz BS clock
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BS = std::ceil(pfd_freq / 50e3);
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if(BS <= 1023) break;
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}
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UHD_ASSERT_THROW(R <= 1023);
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//Reference divide-by-2 for 50% duty cycle
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// if R even, move one divide by 2 to to regs.reference_divide_by_2
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if(R % 2 == 0){
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T = max2870_regs_t::REFERENCE_DIVIDE_BY_2_ENABLED;
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R /= 2;
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}
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//actual frequency calculation
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actual_freq = double((N + (double(FRAC)/double(MOD)))*ref_freq*(1+int(D))/(R*(1+int(T)))/RFdiv);
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boost::uint16_t rx_id = self_base->get_rx_id().to_uint16();
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std::string board_name = (rx_id == 0x0085) ? "CBX-120" : "CBX";
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UHD_LOGV(often)
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<< boost::format("%s Intermediates: ref=%0.2f, outdiv=%f, fbdiv=%f"
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) % board_name.c_str() % (ref_freq*(1+int(D))/(R*(1+int(T)))) % double(RFdiv*2) % double(N + double(FRAC)/double(MOD)) << std::endl
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<< boost::format("%s tune: R=%d, BS=%d, N=%d, FRAC=%d, MOD=%d, T=%d, D=%d, RFdiv=%d, type=%s"
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) % board_name.c_str() % R % BS % N % FRAC % MOD % T % D % RFdiv % ((is_int_n) ? "Integer-N" : "Fractional") << std::endl
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<< boost::format("%s Frequencies (MHz): REQ=%0.2f, ACT=%0.2f, VCO=%0.2f, PFD=%0.2f, BAND=%0.2f"
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) % board_name.c_str() % (target_freq/1e6) % (actual_freq/1e6) % (vco_freq/1e6) % (pfd_freq/1e6) % (pfd_freq/BS/1e6) << std::endl;
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//load the register values
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max2870_regs_t regs;
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if ((unit == dboard_iface::UNIT_TX) and (actual_freq == sbx_tx_lo_2dbm.clip(actual_freq)))
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regs.output_power = max2870_regs_t::OUTPUT_POWER_2DBM;
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else
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regs.output_power = max2870_regs_t::OUTPUT_POWER_5DBM;
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//set frac/int CPL mode
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max2870_regs_t::cpl_t cpl;
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max2870_regs_t::ldf_t ldf;
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max2870_regs_t::cpoc_t cpoc;
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if(is_int_n) {
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cpl = max2870_regs_t::CPL_DISABLED;
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cpoc = max2870_regs_t::CPOC_ENABLED;
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ldf = max2870_regs_t::LDF_INT_N;
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} else {
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cpl = max2870_regs_t::CPL_ENABLED;
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ldf = max2870_regs_t::LDF_FRAC_N;
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cpoc = max2870_regs_t::CPOC_DISABLED;
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}
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regs.frac_12_bit = FRAC;
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regs.int_16_bit = N;
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regs.mod_12_bit = MOD;
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regs.clock_divider_12_bit = std::max(1, int(std::ceil(400e-6*pfd_freq/MOD)));
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regs.feedback_select = (target_freq >= 3.0e9) ? max2870_regs_t::FEEDBACK_SELECT_DIVIDED : max2870_regs_t::FEEDBACK_SELECT_FUNDAMENTAL;
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regs.r_counter_10_bit = R;
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regs.reference_divide_by_2 = T;
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regs.reference_doubler = D;
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regs.band_select_clock_div = BS;
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UHD_ASSERT_THROW(rfdivsel_to_enum.has_key(RFdiv));
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regs.rf_divider_select = rfdivsel_to_enum[RFdiv];
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regs.int_n_mode = (is_int_n) ? max2870_regs_t::INT_N_MODE_INT_N : max2870_regs_t::INT_N_MODE_FRAC_N;
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regs.cpl = cpl;
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regs.ldf = ldf;
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regs.cpoc = cpoc;
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//write the registers
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//correct power-up sequence to write registers (5, 4, 3, 2, 1, 0)
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int addr;
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for(addr=5; addr>=0; addr--){
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UHD_LOGV(often) << boost::format(
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"%s SPI Reg (0x%02x): 0x%08x"
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) % board_name.c_str() % addr % regs.get_reg(addr) << std::endl;
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self_base->get_iface()->write_spi(
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unit, spi_config_t::EDGE_RISE,
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regs.get_reg(addr), 32
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);
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}
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//return the actual frequency
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UHD_LOGV(often) << boost::format(
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"%s tune: actual frequency %f Mhz"
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) % board_name.c_str() % (actual_freq/1e6) << std::endl;
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return actual_freq;
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}
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